System Packet Interface

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The System Packet Interface family of Interoperability Agreements from the Optical Internetworking Forum specify chip-to-chip, channelized, packet interfaces commonly used in synchronous optical networking and ethernet applications. A typical application of such a packet level interface is between a framer (for optical network) or a MAC (for IP network) and a network processor. Another application of this interface might be between a packet processor ASIC and a traffic manager device.

Context[edit]

There are two broad categories of chip-to-chip interfaces. The first, exemplified by PCI-Express and HyperTransport, supports reads and writes of memory addresses. The second broad category carries user packets over 1 or more channels and is exemplified by the IEEE 802.3 family of Media Independent Interfaces and the Optical Internetworking Forum family of System Packet Interfaces. Of these last two, the family of System Packet Interfaces is optimized to carry user packets from many channels. The family of System Packet Interfaces is the most important packet-oriented, chip-to-chip interface family used between devices in the Packet over SONET and Optical Transport Network, which are the principal protocols used to carry the internet between cities.

The term SPI may also refer to a set of low-rate serial communications protocols, not related to optical communications, usually used for transferring data between devices on a printed circuit board; more information may be found here: Serial Peripheral Interface.

Specifications[edit]

The agreements are:

  • SPI-3 – Packet Interface for Physical and Link Layers for OC-48 (2.488 Gbit/s)
  • SPI-4.1 – System Physical Interface Level 4 (SPI-4) Phase 1: A System Interface for Interconnection Between Physical and Link Layer, or Peer-to-Peer Entities Operating at an OC-192 Rate (10 Gbit/s).
  • SPI-4.2 – System Packet Interface Level 4 (SPI-4) Phase 2: OC-192 System Interface for Physical and Link Layer Devices.
  • SPI-5 – Packet Interface for Physical and Link Layers for OC-768 (40 Gbit/s)
  • SPI-S – Scalable System Packet Interface - useful for interfaces starting with OC-48 and scaling into the Terabit range

History of the specifications[edit]

These agreements grew out of the POS-PHY interface definitions PL-3 and PL-4 which themselves came from the ATM Forum's Utopia definitions which had included:

  • Utopia Level 1, an 8 bit, 25 MHz interface supporting OC-3 and slower links (or multiple links aggregating to less than 200 Mbit/s).
  • Utopia Level 2, a 16 bit, 50 MHz interface supporting OC-12 or multiple links aggregating to less than 800 Mbit/s.

System Packet Interface or SPI as it is widely known is a protocol for packet and cell transfers between PHY and LINK layer devices in multi-gigabit applications. This protocol has been developed by Optical Internetworking Forum (OIF) and is fast emerging as one of the most important integration standards in the history of telecommunications and data networking. Devices implementing SPI are typically specified with line rates of 700~800 Mbit/s and in some cases up to 1 Gbit/s. The latest version is SPI 4 Phase 2 also known as SPI 4.2 delivers bandwidth of up to 16 Gbit/s for a 16 bit interface.

Applications[edit]

An example usage of SPI interface is in connecting Network Processors to PHY layer devices. i.e. connecting the MSF of IXP2800 (LINK layer) with IXF framer (PHY layer).

Example:

GigEth---SPI----Network Processor

Technical details[edit]

SPI 4.2[edit]

The SPI 4.2 interface is composed of high speed clock, control, and data lines and lower speed FIFO buffer status lines. The high speed data line include a 16-bit data bus, a 1 bit control line and a double data rate (DDR) clock. The clock can run up to 500 MHz, supporting up to 1 GigaTransfer per second. The FIFO buffer status portion consists of a 2 bit status channel and a clock. SPI 4.2 supports a data width of 16 bits and can be PHY-link, link-link, link-PHY or PHY-PHY connection. The SPI 4.2 interface supports up to 256 port addresses with independent flow control for each.

To ensure optimal use of the rx/tx buffers in devices connected with SPI interface, the RBUF/TBUF element size in those devices should match the SPI-4.2 data burst size.

SPI 4.2 at enhanced rates[edit]

At these high data rates, it becomes more challenging to manage the skew between the clock and data signals. The SPI-4.2 protocol specifies a training sequence which can be used by receivers to correct skew up to +/- 1 bit period. This function is commonly referred to as dynamic phase alignment (DPA).