ARM Cortex-M: Difference between revisions
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* [http://www.arm.com/files/pdf/IntroToCortex-M3.pdf White paper - An Introduction to the ARM Cortex-M3 Processor] |
* [http://www.arm.com/files/pdf/IntroToCortex-M3.pdf White paper - An Introduction to the ARM Cortex-M3 Processor] |
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* [http://arstechnica.com/hardware/news/2008/05/risc-vs-cisc-mobile-era.ars RISC vs. CISC in the mobile era] |
* [http://arstechnica.com/hardware/news/2008/05/risc-vs-cisc-mobile-era.ars RISC vs. CISC in the mobile era] |
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* [http://www.corelis.com/blog/index.php/blog/2011/04/22/cortex-m3-stm32-jtag-embedded-test-jet Cortex-M3/STM32 JTAG Embedded Test] |
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Revision as of 17:33, 18 July 2011
| General information | |
|---|---|
| Designed by | ARM |
| Architecture and classification | |
| Instruction set | ARMv7-M |
The ARM Cortex-M3 is a processor.
Features
Key features of the Cortex-M3 core are[1]:
- Architecture: ARMv7-M (Harvard)
- ISA Support: Thumb / Thumb-2
- Pipeline: 3-Stage + branch speculation
- Interrupts: NMI + 1 to 240 Physical Interrupts
- Interrupt Latency: 12 Cycles
- Sleep Modes: Integrated
- Memory Protection: 8 region Memory Protection Unit
- Dhrystone Rating: 1.25 DMIPS/MHz
- Power Consumption: 0.19mW/MHz
- Area: 0.86mm2 (Core & Peripherals)
Implementations
Several system-on-a-chips are implementing the Cortex-M3 core, including:
- NXP: 17xx and 13xx families
- Texas Instruments: Stellaris family
- ST Microelecctronics: STM32 family
- Atmel: SAM3S, SAM3U and SAM3N families
See also
References
External links
- ARM Cortex-M3 - ARM Processor
- White paper - An Introduction to the ARM Cortex-M3 Processor
- RISC vs. CISC in the mobile era
- Cortex-M3/STM32 JTAG Embedded Test
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