High-level verification

High-level verification (HLV), is a companion design methodology and technology to High-level synthesis

Electronic digital hardware design has evolved from low level abstraction at gate level to register transfer level (RTL), the abstraction level above RTL is commonly called high-level, ESL, or behavioral/algorithmic level.

In High-level synthesis, behavioral/algorithmic designs in ANSI C/C++/SystemC code is synthesized to RTL, which is then synthesized into gate level through logic synthesis. Functional verification is the task to make sure a design at RTL or gate level conforms to a specification. As logic synthesis matures, most functional verification is done at the higher abstraction, i.e. at RTL level, the correctness of logic synthesis tool in the translating process from RTL description to gate netlist is a less concern today.

High-level synthesis is still an emerging technology, so High-level verification today still has two important areas under development: 1) to validate HLS is correct in the translation process, i.e. to validate the design before and after HLS are equivalent 2) to verify a design in ANSI C/C++/SystemC code is conforming to a specification.

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See Also

Electronic System Level
SystemC
Transaction-level modeling
Functional verification

External Links

OSCI ( Open SystemC Initiative )

--Veralift (talk) 18:46, 10 August 2009 (UTC)