Talk:Sandy Bridge

Teraflop processor

http://news.com.com/Intel+pledges+80+cores+in+five+years/2100-1006_3-6119618.html?tag=nefd.top

there might be a correlation.

Intel pledges 80 cores in 5 years. that's right aroudn the proper time period. Based on that ti would not be unreasonable to speculate that Intel would be using 20 through 40+ core on Gesher.

pure speculation though

No, the teraflop 80-core processor is a completely different beast that has very little to do with Gesher. See http://www.dailytech.com/Intel+Takes+the+Hood+Off+TeraScale+Computing/article6057.htm. Gesher will the evolutionary based on an evolved formed of the Core 2 Duo, while the teraflop chip is revolutionary, just as Conroe was revolutionary after NetBurst. --Conquerist 23:25, 3 March 2007 (UTC)

Found a contradiction in the node size

The main Intel Core 2 article, currently under the Successors heading, claims that the size is speculative and may be at 22 nm (with Nehalem possibly at 32 nm), while this article is toned in a way to not only make it sound more definite, but also that it's to be a 32 nm size. I'm not sure if it's speculation in this article as well, and in that case it needs to be marked so, and preferrably also agree with the other Wikipedia article. :-) -- Northgrove 15:48, 31 January 2007 (UTC)

The Core 2 article now states that Gesher will be based on the 32 nm process. Additionally, I have cited that Gesher is 32 nm both in this article and in the Core 2 Article. --Conquerist 23:25, 3 March 2007 (UTC)

Rename article?

Shouldn't the article be renamaed to "Sandy Bridge (microarchitecture)" (together with the Nehalem (CPU architecture) and Intel Core (CPU architecture) articles) to avoid using the word "architecture" for microarchitecture (hardware) and instruction set (software) possibly confusing a bit?

I suggested on Talk:Nehalem (CPU architecture) that we rename Intel Core (CPU architecture), Nehalem (CPU architecture), and Sandy Bridge (CPU architecture) to "Intel Core (CPU microarchitecture)", "Nehalem (CPU microarchitecture)", and "Sandy Bridge (CPU microarchitecture)". My reason is that the terms "architecture" and "microarchitecture" refer to different things. "Architecture" is for the overall design of the processor (as in the ISA), such as x86, POWER, Alpha, SPARC, etc. Microarchitecture, on the other hand, refers to the specific implementation of the design. CPUs with different architectures are not compatible, but those with different microarchitectures are compatible. That's my idea, what do you think? (And yes, I just copied this post from Talk:Intel Core (CPU architecture)) Imperator3733 23:50, 24 September 2007 (UTC)

I mentioned at Talk:Intel Core (CPU architecture) a new, revised idea for renaming these articles. The idea is to rename the articles to Intel Core (microarchitecture), Nehalem (microarchitecture), and Sandy Bridge (microarchitecture). Another possibility would be to have "Intel" in all the names (making the naming more consistent -- i.e. Intel Nehalem (microarchitecture) and Intel Sandy Bridge (microarchitecture). If we do that I would suggest making the change to other uArch pages (i.e. NetBurst to Intel NetBurst (microarchitecture), Intel P6 to Intel P6 (microarchitecture), etc). What do you think? I'll give this a week for comments. If the response is favorable, I (or someone else) will/can rename them. If there is no response, I'll probably wait a bit longer. If anyone sees this, please respond. Thank you. -- Imperator3733 00:22, 16 October 2007 (UTC)

The pages have now been renamed. See Intel Core (microarchitecture), Nehalem (microarchitecture), and Sandy Bridge (microarchitecture) -- Imperator3733 18:06, 24 October 2007 (UTC)

Tick-tock?

Can someone change this term to something un-jargony? —Preceding unsigned comment added by Alwayswiththequestions (talk • contribs) 22:36, 5 January 2008 (UTC)

Tick means a shrink to a smaller process technology, with minor changes to the design. Tock means a major design change on the same process as the previous Tick. For more information, see Intel Tick Tock. -- Imperator3733 (talk) 16:52, 21 February 2008 (UTC)

What platform will Sandy Bridge be released on? And where does the Montevina platform (2008) fit in the tick-tock model? Or can a new platform be released any time? But then, isn't there also supposed to be such model for platforms?

1. Tock - Intel Core microarchitecture
2. Tick - Shrink/derivative (Penryn)
3. Tock - New Intel microarchitecture (Nehalem)

-- 83.101.9.165 (talk) 17:50, 27 February 2008 (UTC)

Montevina uses Penryn processors, so it would be a Tick. I'm guessing that Sandy Bridge would use a similar platform to that used by Nehalem (QPI/PCIe), but I don't know for sure. -- Imperator3733 (talk) 21:48, 27 February 2008 (UTC)

AMD's instruction sets and Intel?

Will Sandy Bridge contain SSE5, MMX+, 3DNow! and 3DNow!+ instruction sets? Please, add that info also to the main article. Urvabara (talk) 11:37, 21 February 2008 (UTC)

I'm not sure, but I think 3DNow! and 3DNow!+ are pretty much obsolete. Intel has never supported those instruction sets, so I don't think they would do so with Sandy Bridge. I have never heard of MMX+ -- could you please link to some information on it? I don't know if SSE5 will be included -- the time frames work out, but there haven't been any announcements one way or the other (I think). -- Imperator3733 (talk) 16:49, 21 February 2008 (UTC)

See this picture [1]. See also [2] and [3]. Is there any way to contact Intel engineers? I would like to know why not to support AMD instruction sets. Urvabara (talk) 16:03, 22 February 2008 (UTC)

That's the first time I've ever seen anything on MMX+. I guess its just integer SSE, so it seems to me that Intel probably supports those instructions (I think SSE2 added integer instructions).

As far as contacting Intel engineers, Intel doesn't publish contact information for its employees, but it does say that the email format is generally first.last@intel.com or first.middle_inital.last@intel.com (I think I'm remembering that correctly). Of course you have to know an employees name before you can use that. You could always try using Intel's "Contact Us" page, but my experience with that has been pretty bad. First they try an automated response that tries to analyze your message to provide possible links to your question (which has never worked for me), and then you need to escalate your question to a human. I have never gotten a satisfactory answer from them, but maybe you will. Good luck. -- Imperator3733 (talk) 22:17, 27 February 2008 (UTC)

Thanks! Urvabara (talk) 08:06, 28 February 2008 (UTC)

Processor roadmaps

I've started a discussion on the processor roadmap graphics over at Talk:Nehalem (microarchitecture)#Processor roadmaps. Please take a look and make a comment if you have any thoughts. Thank you. -- Imperator3733 (talk) 15:06, 11 June 2008 (UTC)

Keifer

Should the section on Keifer even be in this article? It doesn't seem like it fits. -- Imperator3733 (talk) 18:41, 2 July 2008 (UTC)

i agree, it seems irrelevant and should be removedNicoli nicolivich (talk) 00:21, 16 November 2008 (UTC)

Socket for Sandy Bridge

It is probably much too early to speculate, but I wonder if Intel will be using LGA1366 for Sandy Bridge? I know Westmere should be using it, but I am quite curious as to Sandy Bridge. LGA775 supported P4 up to Core 2, and LGA1366 would seem to be able to support a processor such as Sandy Bridge--though I am not so sure about the apparent bus improvements. --Marsbound2024 (talk) 01:08, 23 November 2008 (UTC)

Translation Lookaside Buffer Cache.

Does anyone know the TLB cache size of Sandy Bridge ? For some reason this information is impossible to find - and it is very important for large applications.

Is it per die ? Per core ? Per hyper thread ? —Preceding unsigned comment added by 82.95.66.103 (talk) 18:38, 13 December 2009 (UTC)

Contradiction in L2 size

The article says (in the bullet points) that Sandy Bridge will have 2048KB of L2 per core, while the table at the end of the article says it will have 256KB of L2 per core. 2048KB L2 seems a bit unrealistic. Nehalem only has 256KB.

-- ssj4Gogeta

Any Idea where this came from

"Nehalem may stay at the server platform while Sandy Bridge is released for the mobile segments, which would split the markets into two CPU lines."

This statement is highly speculative. The article mentions it might be split but does not indicate it will be split or indicate segments splitting. High-end chip (servers & gaming PC) tend to get the best margins so rarely will they not get the latest and greatest first. Mobile segments tend to be a follow on a few months later with mainstream and value chips holding up the rear. Did who ever write this in speak the language natively since machine translations can be problematic. In any case most of the items from the PC watch section should be reviewed after IDF in april. —Preceding unsigned comment added by 98.162.247.51 (talk) 07:17, 11 March 2010 (UTC)

The 4P and 1-2P isn't consistent

I really doubt the Sandy Bridge EX CPU will be just 4 sockets at most, because Nehalem EX clearly was also for more than 4 sockets, 8 or more. This should be replaced with MP (multiprocessor). The 1-2P also is not consistent because it doesn't differ UP (Uni-processor) or DP (Dual processor).Jasper Deng (talk) 03:07, 1 April 2010 (UTC)

Intel will split the EX market into two sections. Westmere-EX and then Ivy Bridge-EX-A succeed Nehalem-EX in the high-end of that market, while Sandy Bridge-EX and Ivy Bridge-EX-B succeed Nehalem-EX in the low-end of that market. 76.192.138.36 (talk) 20:28, 30 April 2010 (UTC)

References

PCWatch isn't a good citation for CPUs as they were purely speculative. In addition I see no reference saying that Sandy Bridge EX is limited to 4 sockets. Also one of the references has been taken down (the link is now broken). —Preceding unsigned comment added by Jasper Deng (talk • contribs) 03:13, 1 April 2010 (UTC)

Article is out of date regarding socket 1356.

Sandy Bridge will be released Q1 2011 for socket 1155 and the high-end will be released Q3 2011 on socket 2011.

Socket 1356 has been scrapped, and the table needs to be updated as such.

according to pcmag. the release date according to intel is q4 2010 -Tracer9999 (talk) 10:56, 29 April 2010 (UTC)

Link for socket 1356? And that PC Mag article says Q4 2010 for production, not release. 76.192.138.36 (talk) 20:28, 30 April 2010 (UTC)

Edit: It says production and shipping 76.192.138.36 (talk) 20:30, 30 April 2010 (UTC)

http://www.bit-tech.net/hardware/cpus/2010/04/21/intel-sandy-bridge-details-of-the-next-gen/

http://vr-zone.com/articles/a-look-into-intel-s-next-gen-enthusiast-platform--sandy-bridge-e--waimea-bay/8877-1.html%7Ctitle=New

Both of these recent articles have no mention of 1356, but do mention 2011 for the highend desktop space and 1155 for the mainstream. Q4 2010 is stated as possible, but up to change.

Update variants table PLEASE!

This table has been quite out of date, and no-one's fixing it. I don't have the time to fix it. Can someone please fix it? Or shall we delete this section due to insufficient citations?Jasper Deng (talk) 02:38, 4 May 2010 (UTC)

Continued vandalism by 75.57.77.40

I'm not sure of the proper procedure, but this IP continues to edit the technical specs into unprecedented values without source, and continues to edit them despite reversion. —Preceding unsigned comment added by 98.27.85.106 (talk) 21:46, 27 May 2010 (UTC)

The same user evidently also vandalized other pages, and used at least two addresses, see Special:Contributions/75.57.77.40 and Special:Contributions/75.57.67.43. Arndbergmann (talk) 01:24, 28 May 2010 (UTC)

32-core and 50+-core Sandy Bridge chips

http://www.itworld.com/hardware/109481/intel-unveils-new-server-chip-32-cores

Intel unveiled 32-core chips for servers. These chips were said to be part of the Sandy Bridge microarchitecture. —Preceding unsigned comment added by Jasper Deng (talk • contribs) 16:52, 31 May 2010 (UTC)

According to [4], these chips are Larrabee, not Sandy Bridge. Indeed, putting that many general purpose cores on one chip would make the size explode even at 22 nm, so a simplified larrabee core seems much more plausible. Arndbergmann (talk) 21:11, 31 May 2010 (UTC)

Transition

The article currently says: "If the transition to 32 nm is difficult, then Sandy Bridge may go over three generations (Sandy Bridge, Ivy Bridge, and another Bridge) as opposed to two with Core 2 and Nehalem."

Somehow, I think this doesn't make much sense. Why should a transition to 32nm influence things if the architecture starts out at 32nm ?!?

Also, the article linked as source for this seems to talk a LOT about the transition to 22nm. I think this is currently wrong in the wikipedia page and "32 nm" in the sentence should be fixed to "22 nm". —Preceding unsigned comment added by 93.203.214.239 (talk) 12:38, 7 June 2010 (UTC)

Confusing spec item about SSE

There's at main page said:

The specifications are reported to be as follows:

* ......
* Without SSE: 8 DP GFLOPS/core (2 DP FP/clock), 32 DP GFLOPS per processor.
* With AVX: 32 DP GFLOPS/core (8 DP FP/clock), 128 DP GFLOPS/processor.

And from this follows that it does not support SSE, but support AVX.

Maybe it's not what was implied by that phrase, but this is the meaning it delivers.

And it's not true, since it will support all previous instructions including SSE + new AVX instructions.

GFLOPS should be removed from spec list, and those two items changed to something like:

* it will support SSE (and all other previous instructions) + new AVX instructions

or simply

* it will support new AVX instructions  —Preceding unsigned comment added by 93.73.4.74 (talk) 14:28, 12 September 2010 (UTC) 

L1 and L2 cache latency correction

A new extensive article about Sandy Bridge architecture (http://www.realworldtech.com/page.cfm?ArticleID=RWT091810191937&p=7) points to different values for L1 and L2 cache load-to-use latencies, as follows:

L1 is 4 cycle (same as Nehalem), not 3.
L2 is 12 cycles, not 8.

--Fellix 15:08, 27 September 2010 (UTC) —Preceding unsigned comment added by Fellix (talk • contribs)

More News on the Sandy Bridge

Hi everyone,

I am brand new to Wikipedia, and really hope I am not messing anything up with my first discussion post here. I "joined" because I saw the last edit to this area was September 27, 2010 and there's been a great deal going on in various technical discussion boards that I participate in on a daily basis.

I'm not sure how often the group here convenes to discuss what to put in, remove, or edit from the main article. I'm also not sure how to cite sources like you have done, but I am reading up on it. I'd like to offer new material rather than correct some mistakes I see (people often hate having their errors pointed out) so I'd like the discussion to focus on what is not in the article right now that I think would benefit by being brought into the fold.

How does that sounds?

Thanks in advance.

Bit XOR or NAND (talk) 02:22, 8 November 2010 (UTC)

Moved information from "Architecture" into a separate "Overclocking" area. Added more info from press releases in September 2010 from ZD Net (reliable media source).

Bit XOR or NAND (talk) 22:55, 10 November 2010 (UTC)

In general there is no meaningful coordination before editing except on articles with severe problems or where major changes are being made. If you think something should be changed, be bold (but be prepared to discuss if someone else disagrees). And please correct anything that is factually inaccurate. It's unlikely you'll bruise anyone's ego (they are unlikely even to notice the edit), and if their ego does get bruised then they deserved it. — Aluvus t/c 07:52, 11 November 2010 (UTC)