Talk:OpenRISC 1200: Difference between revisions
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== Performance == |
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I'm not sure the performance figures are at all helpful, and in the absence of a citation, I find them very hard to believe. The OpenRISC typically runs on FPGA's clocked at 25-50MHz, although the latest FPGAs can wind that up closer to 100MHz. There are known issues with the implementation of the caches and MMUs that constrain performance. [[User:Jeremybennett|Jeremybennett]] ([[User talk:Jeremybennett|talk]]) 19:53, 24 October 2011 (UTC) |
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== History == |
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The history section was wrong, reflecting a confusion between the OpenRISC 1000 (which is an architectural specification for a family of processors) and the OpenRISC 1200 which was the first implementation of that architecture. Text corrected. [[User:Jeremybennett|Jeremybennett]] ([[User talk:Jeremybennett|talk]]) 19:49, 24 October 2011 (UTC) |
The history section was wrong, reflecting a confusion between the OpenRISC 1000 (which is an architectural specification for a family of processors) and the OpenRISC 1200 which was the first implementation of that architecture. Text corrected. [[User:Jeremybennett|Jeremybennett]] ([[User talk:Jeremybennett|talk]]) 19:49, 24 October 2011 (UTC) |
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Revision as of 19:53, 24 October 2011
Performance
I'm not sure the performance figures are at all helpful, and in the absence of a citation, I find them very hard to believe. The OpenRISC typically runs on FPGA's clocked at 25-50MHz, although the latest FPGAs can wind that up closer to 100MHz. There are known issues with the implementation of the caches and MMUs that constrain performance. Jeremybennett (talk) 19:53, 24 October 2011 (UTC)
History
The history section was wrong, reflecting a confusion between the OpenRISC 1000 (which is an architectural specification for a family of processors) and the OpenRISC 1200 which was the first implementation of that architecture. Text corrected. Jeremybennett (talk) 19:49, 24 October 2011 (UTC)