Power Processing Element: Difference between revisions
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The Power Processing Element is an In-Order processor, but it has some unique traits which allow it to achieve some benefits of Out-of-Order execution without expensive re-ordering hardware. Upon reaching an L1 cache miss - it can execute past the cache miss, stopping only when an instruction is actually dependent on a load. It can send up to 8 load instructions to the L2 cache out-of-order. It also has an instruction delay pipe - a side path that allows it to execute instructions that would normally cause pipeline stalls without holding up the rest of the pipeline. |
The Power Processing Element is an In-Order processor, but it has some unique traits which allow it to achieve some benefits of Out-of-Order execution without expensive re-ordering hardware. Upon reaching an L1 cache miss - it can execute past the cache miss, stopping only when an instruction is actually dependent on a load. It can send up to 8 load instructions to the L2 cache out-of-order. It also has an instruction delay pipe - a side path that allows it to execute instructions that would normally cause pipeline stalls without holding up the rest of the pipeline. |
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== Like a Dual-Core Processor == |
== Like a Dual-Core Processor == |
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Revision as of 03:17, 4 February 2014
 | This article needs additional citations for verification. (February 2014) |
The Power Processing Element is a microprocessor designed by IBM for use primarily in the game consoles Playstation 3 and Xbox 360. It is a 64-bit, dual-threaded, PowerPC architecture.
Main features
- 64-bit, dual-threaded
- 3.2 GHZ clockrate
- 32 KB L1 Instruction Cache
- 32 KB L1 Data Cache
- 512 KB Unified L2 Cache, 8-way set associative
- Compatible with PowerPC 970 MP/FX applications
- Includes Altivec multimedia extensions
Functional units
- Branch Unit (BRU)
- Fixed Point Integer Unit (FXU)
- Load and Store Unit (LSU)
- Floating-Point Unit (FPU)
- Vector Media Extension Unit (VMX)
In-Order
The Power Processing Element is an In-Order processor, but it has some unique traits which allow it to achieve some benefits of Out-of-Order execution without expensive re-ordering hardware. Upon reaching an L1 cache miss - it can execute past the cache miss, stopping only when an instruction is actually dependent on a load. It can send up to 8 load instructions to the L2 cache out-of-order. It also has an instruction delay pipe - a side path that allows it to execute instructions that would normally cause pipeline stalls without holding up the rest of the pipeline.
Like a Dual-Core Processor
It can run two threads simultaneously. The main registers for code execution are duplicated, as are the exception and interrupt-handling registers, and several essential arrays and queues. They can generate exceptions simultaneously, and perform branch prediction on their individual branch histories. The execution engine and caches are not duplicated though - so it is still just a single-core design.[1]
Floating Point Capacity
Its 64-bit floating-point unit, and 128-bit VMX unit, can perform a theoretical 12 floating-point operations per cycle, as all IBM PowerPC floating-point units can do floating-point mulitply-adds, and come no smaller then 64-bits. That gives 3.2 billion clock cycles * 12 = 38.4 billion floating-point operations/second.