Talk:I486SX

IMHO the 486 SX was not a 486 Dx with a defective fpu. It was a marketing creation a 486 DX with afpu disabled same production costs but less features.

As so far as I've read, the SX actually had higher production costs than a DX, and that it was sold to try and compete with AMD's midend space. Either way, the SX chips were horrendously slow.

I disagree. Intel certainly said at the time that the FPUs were tested and disabled if not functional. This fits in well with contemporary industry observations that they initially had great difficulty ramping up the yield of the 486DX. As for performance, if running with a 32 bit bus (it could be configured to run with a 16 bit bus like the 386SX), it was identical to a similarly clocked 486 if floating point calculations were not used. CrispMuncher (talk) 14:49, 18 July 2008 (UTC)

CrispMuncher I saw your undo of my edit and your comment. I'm not sure how these disagreements get resolved on Wikipedia. I was a product engineer for the i486DX and the first two versions of the i486SX and I managed the small design project for the first 486SX in a plastic package. I wrote the programs that tested the chips in production worldwide so I can tell you for a fact that is not true that units were built according to whether the FPU passed. And I can tell you that a laser did not disconnect the FPU. It was a bond pad that had a bondwire tied to power or ground that disabled the FPU. You mention an Intel cite that supports your point - please point to it. You are also wrong about the CPUID - it did exist. See for example this cite. http://www.gilanet.com/david/Intel486.htm. I was intimately familar with those numbers at the time and those look right to me. So where do we go from here? Awitko (talk) 23:51, 3 November 2008 (UTC)awitko

I'll dig out a cite in the next day or two, but your edit itself admitted the existence of public statements that this was the case. I'm sure I can find a contemporary press release, datasheet or whatever but that means going up in my loft which I'm not doing tonight. Regarding the CPUID instruction, your reference actually confirms my assertion - CPUID was introduced in 1992 whereas the 486SX was introduced a year earlier. My memory was that later steppings introduced the instruction but according to http://www.intel.com/Assets/PDF/appnote/241618.pdf (page 21, and footnotes on page 23) the CPUID instruction never made it to the 486SX line. It's possible this is a simplification and it did appear on some chips, but given that the troublesome statements are already limited to early chips then any discussion of CPUID is obviously an irrelevance.

That is the key point to bear in mind - those comments relate to early examples. I don't assert that there were no later chips which were intended from the beginning to be SXes and lacked an FPU altogether. Given your experience I would be a fool to argue about your knowledge of particular steppings, and certainly I'm sure you have much to add on this article of benefit. However, is it possible that you are mistaken over dates? If the particular designs you were working on were later on in the 486-on-the-desktop period things could easily have changed by the time you started those particular projects. Finally, one of the weaknesses of Wikipedia is that sources are needed for contentious material. Expert opinion such as your own is welcome but still needs to be backed up by publically available information. CrispMuncher (talk) 20:13, 4 November 2008 (UTC)

The version you describe is plastered all over the internet, but it is simply untrue. Absolutely, no doubt. The problem is that this was an internal implementation issue that Intel had no interest in discussing publicly so I am virtually certain you won't find anything in official Intel literature. I was at Intel from 1988 to 1999. I was on the debug team for the original i486DX. The original i486DX had the disable floating point (DFP) pad from the beginning. I think it was initially conceived as a debug option and only later did Intel decided to use it to segment the market. I was involved on the original i486SX from the very beginning. I was on a team of about 12 that were recognized for the implementation of the original i486SX. I was involved in both versions that had an FPU and we always disabled using a bond wire option. And versions after I was involved had the FPU removed. As far as the CPUID, the reference shows CPUID for the early versions of the i486DX which go back to 1989 so that definitely predated the introduction of the i486SX. How the CPUID was accessed is not really relevant here, but although there may not have been an instruction at the time (I can't remember), there was a way to get the CPUID on the databus. For example, when I designed the i486SX for the plastic package, I started with a process shrink version of the i486DX and one of the several changes I made was to change the hardwired CPUID.

Crispmuncher. If you look on page 11 of your appnote you will see it state: "Later, with the advent of the Intel386 processor, Intel implemented processor signature identification that provided the processor family, model, and stepping numbers to software, but only upon reset." So the CPUID was accessable for the 486SX without using the CPUID instruction. Also, if you look at http://www.intel.com/pressroom/kits/quickreffam.htm#i486 at the last page you will see a reference to 486SX versions with (1) 1.2 million transistors on a 1.0 micron process which is the same number of transistors at the 80486DX listed there (thus this version is the one with a FPU that was disabled) and (2) 0.9 million transistors on a 0.8 micron process (this is the one with the FPU removed). I worked on an interim product in the PQFP package that had 1.2 million transistors on the 0.8 micron process - which is not listed there. Awitko (talk) 04:48, 10 November 2008 (UTC)

Crispmuncher. I also want to address your earlier point about i486DX yields. I gather than you believe the motivation behind the i486SX was to salvage defective units during i486DX manufacturing. The i486SX was announced about 20 months after production 486DX units started shipping. At that point, we were running high volumes and had good yields. The motivation behind the i486SX was price discrimination. We could compete with the mid-range AMD product using our lower performance i486SX without having to compromise pricing on our high end i486DX product. You find price discrimination as a way to increase profits in many businesses. Think first class and coach tickets on airlines. If all seats were first class, many of the coach customers would be lost. If all seats were coach, they would lose the premium that the first class customers would have been willing to pay. It works even if the differences in prices have little or nothing to do with the cost of providing the different levels of service. For example, Vista Home, Professional, and Ultimate are three products that have different prices but all three cost Microsoft the same amount to produce. The i486SX strategy also allowed us to sell highly profitable i487 upgrade chips to end users that wanted to add FPU capability to their i486SX PC. Awitko (talk) 17:41, 10 November 2008 (UTC)

And I don't know the origin of the story that i486SX units had defective FPU units that were permanently disconnected by laser. It was certainly convenient for Intel that people believed it. For the early i486SX in a PGA package, one could flip the lid off the package and. if they had a steady hand and knew which bond pad disabled the FPU, they could disconnect the bondwire to reenable the FPU. They probably could have identified the bond pad by comparing the bond wires of an i486DX and an i486SX on the same process (same die size). The chip would still have a CPUID that identifed it as a i486SX - which probably would have caused problems with some software recognizing that an FPU was available, but it would have an enabled FPU like the i486DX. Some of the FPUs would not work because they had not been tested, but many of them would work. The lack of testing did not stop people from overclocking CPUa to run at higher operating frequencies than tested by Intel. Many would have been happy to make that modification to save hundreds of dollars on the i486DX or i487 upgrade. Of course, Intel would not have liked that. BTW, this modification could only have been done in the early units - it could not have been done in the i486SX units that were in a plastic package (not accessible) or the ones with the FPU removed (not available!). Awitko (talk) 19:36, 10 November 2008 (UTC)