Talk:Verilog

Not like C

Mostly a good writeup, with lots of great background info. I have one big issue with it, though: Why do folks always say that Verilog syntax is "reminiscent" of C? It looks, feels, and works almost nothing like C...

If you're comparing "VHDL vs. Verilog", it might be a workable analogy to say that's like "Pascal vs. C" in some ways, but that's where the similarity ends.

Also, the current text says that "it differs from C primarily in how the language represents literals and the ability to deal with time." Ignoring how the syntax is nothing at all like C except for begin statement-followed-by-semicolon, this completely discounts how verilog executes all top-level statements in *parallel*, which is one of the major features of any HDL.

Verilog is actually more like Pascal (from which Verilog borrows the begin ... end and the function definition styles) than it is like C. 158.140.1.25 02:56, 23 January 2007 (UTC)[reply]

Sure, some of the statements like:

 wire foo;

might look sort of like C (or a billion other languages that do declarations that way!) but most of verilog is nothing at all like C in syntax or feel. And it's not just begin/end versus curly-braces... function declaration is entirely different, switch statements use a totally different syntax and have different semantics ... and on and on ...

Anyone else have an opinion on this? I've never met anyone who *actually* thought that writing verilog was anything like writing C. Everyone pretty much parrots that verilog is "C-like" or has "C-like syntax", but when you call them on it, nobody seems to really believe it or know where they original heard that from...

I agree with you that Verilog bears only faint resemblance to C. According to what I've read, the authors of Verilog wanted a language that looked like C so it would be more familiar to engineers. It has the ternary operator, the basic math and logic operators, case sensitive variable names, and semicolon terminating (many) statements. But that's where the similarity ends. If they wanted to have it C-like they should have kept the curly brackets instead of using begin/end, kept the syntax of the switch statement, and made the declaration syntax more C like. --69.5.156.155 00:19, 10 Dec 2004 (UTC)

In example code (counter):

 :
 //enable CEP is a clock enable only
 //enable CET is a clock enable and enables the TC output
 :
 if (cet && cep) // This simulates the enables both being true

following sentences might be possibly appropriate ?

 if (cet || cep) // This simulates the enables either being true

Sinar 12:43, 27 August 2005 (UTC)[reply]

Can you give an example code where Verilog Resembles Pascal Code? 134.50.25.39 (talk) 16:45, 10 September 2008 (UTC)[reply]

Is constant section correct?

I think the binary constant example is incorrect. As I am not an expert, I have not changed the page, but I am asking the question. I believe 4'b1010 is binary 1010, 4 bits wide, decimal value 10.

207.212.81.42 23:40, 7 February 2006 (UTC)Alan]][reply]

We need to check on the sign extension capabilities here. The example in the article states that a 20'd44 has a zero extension but what happens if I want to do a negative number? What is the default response of Verilog? Adam Arnesen (talk) 18:59, 5 June 2008 (UTC)[reply]

Links to external tools

User:Mikkalai removed all references to external tools. I see that a partial restoration has been done. However, one of the links seems more than a little dubious: "The most popular free Verilog simulator for Windows.". It is only "free" in a temporary closed-source model. Described on the vendor's website as an "evaluation version". So there are 2 issues: 1. Is it "free" and 2. what evidence is there that it is the "most popular"?

Too many examples

This page has too many god damn examples. We need a conscise summary, not a list of examples that give, by and large, an incomplete understanding of the language. Fresheneesz 07:04, 19 October 2006 (UTC)[reply]

I agree, especially in regards to the "Hello World" example. Their is no purpose in writing a "program" like the example illustrates, because Verilog is not a programming language. Yossarianisdead 04:54, 26 January 2007 (UTC)[reply]

I want to second Yossarianisdead on the "Hello World" example. When you see a "Hello World" program you immediately think programming. You would very rarely use Verilog to print Hello World. Adam Arnesen (talk) 18:54, 5 June 2008 (UTC)[reply]

Constants (literals) need not have sizes

The text and the examples give the impression that constant literals must have a bit width as part of their syntax. this is not correct. For example, 'b1010 is perfectly valid, and is distinct from 4'b1010. In fact, "10" is a perfectly valid literal even without the base.

Steveicarus 05:34, 7 January 2007 (UTC)[reply]

Yes, the text does give this impression, however, it is with good reason. If the bit width is not given, then the default is 32bits. If the base is not given, then the default is decimal. The fact that the constant literals: 'b10, 2'b10, and 10 are all different and distinct highlights the importance of using these optional fields. The only time I would think not using the bit width and or base fields would be warranted is when the intended constant literal is 32bits and or a decimal value. I believe the current text should be updated to indicate the optionality of these fields and the defaults assumed in their absence. Yossarianisdead 00:30, 17 February 2007 (UTC)[reply]

The default value is not 32 bits, but some compiler specific width more than 32 bits. In fact, I do not believe the standard says that unsized literals must have any fixed size; only that they must not be truncated to less then 32 bits.

The standard does say that "integer" variables have a fixed bit width, but again it does not say what that width is, other then that it must be at least 32 bits wide.

In any case, it is most certainly and easily verifiably obvious that explicit bit widths are not required in the syntax for literals. Steveicarus 00:50, 4 March 2007 (UTC)[reply]

Problem with History

Verilog was initialling designed as a gate level simulator not an HDL. As I recall the original LRM from Gateway contained about 24 chapters. One chapter, chapter 8 as I recall, described the constructs we currently use today as the HDL part of the language. My recollection is that Verilog became an HDL when Synopsys chose the chapter 8 constructs as the basis for their software tool, Design Compiler, to generate gates from RTL description. They didn't support VHDL until much later. Before that the chapter 8 constructs were primarily used for describing verification code to stimulate and evaluate gate level designs, a function usually referred to as a Testbench. Originally Verilog was an interpreted language, had twelve states for its logical values such as supply, strong, weak and high impedance each applied to one, zero and unknown. Very useful for old NMOS based gate level designs that often included wired-and and wired-or constructs. The original verilog primitives include and, or, nand, nor gates and even pmos and nmos transistor primitives. It also included the ability to create user defined gate level primitives via the user defined primitive (udp) feature. I believe some of these original capabilites still exist in the Verilog-XL simulator. By the way, the XL stands for "accellerated" and applied to an increase in gate level simulation performance, i.e. Cadence added an engine to the interpretor that increased the performance of simulation for those parts of a design fully described by the gate level primitives and complient udp. I also remember that prior to Verilog was a gate level simulator called ilogs, I think, that was very similar to, if not the same, as Verilog but without the chapter 8 verification constructs and maybe a couple of other features. In those days, the late 1980's, we primarily entered our digital designs using schematic editors referencing libraries of gates, flops and transistors. We ran netlistors on these graphical entries to create structural netlists that referenced Verilog primitives and udps. We added a testbench of chapter 8 code for imulation and verification. —Preceding unsigned comment added by Mgravenstein (talk • contribs) 19:57, 13 October 2008 (UTC)[reply]

Synthesizeable constructs

Is it just me or does the "Synthesizeable constructs" section say absolutely nothing about which constructs are synthesizable? Am I to assume that all examples given in that section are synthesizable? If so, what *isn't* synthesizable? I'm just embarking on learning Verilog, FWIW... 123.243.228.66 (talk) 12:28, 14 January 2009 (UTC)[reply]