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FMA3 instruction set

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The FMA or FMA3 instruction set is a future extension to the 128-bit SIMD instructions in the X86 instruction set proposed by Intel in December 2008.

FMA3 is a revision of the previously specified FMA(4)[1]. In the meantime, AMD have started to plan support for FMA4.

New instructions

The FMA3 instruction set contains fused multiply-and-add instructions for floating point scalar and SIMD operations.

Compatibility issue

The incompatibility between FMA3 and FMA4 concerns the issue of whether the instruction can have three or four different operands. The fused multiply-add operation has the form:

The 4-operand form (FMA4) allows a, b, c and d to be four different registers, while the 3-operand form (FMA3) requires that d is the same register as either a, b or c. The 3-operand form makes the code shorter and the hardware implementation slightly simpler.

CPUs with FMA3

  • Intel
    • Intel will introduce hardware FMA (fused multiply-add) in 2011 (or later)[2]. These instructions may arrive with the 22 nm process, also slated for 2011.
  • AMD
    • AMD will support FMA3 in the future for compatibility reasons if Intel sticks to FMA3 only[3].

Timeline

  • August 2007: AMD announces the SSE5 instruction set, which includes 3-operand fused multiply-add instructions. A new coding scheme (DREX) is introduced for allowing instructions to have three operands [4].
  • April 2008: Intel announces their AVX and FMA instruction sets, including 4-operand fused multiply-add instructions. The coding of these instructions uses the new VEX coding scheme which is more flexible than AMD's DREX scheme [5].
  • December 2008: Intel changes the specification for their FMA instructions from 4-operand to 3-operand instructions. The VEX coding scheme is still used [6].
  • May 2009: AMD changes the specification of their FMA instructions from the 3-operand DREX form to the 4-operand VEX form, compatible with the April 2008 Intel specification rather than the December 2008 Intel specification[7].

It is currently uncertain whether the 3-operand VEX coded form (which we may call FMA3) or the 4-operand form (FMA4) will be the dominating standard in the future. It is also possible that future processors will support both forms.

See also

References

  1. ^ "Intel Advanced Vector Extensions Programming Reference" (PDF). Intel. Retrieved 2008-04-05.
  2. ^ Template:Ja iconPC Watch - Intel Roadmap: a break away from x86 (April 7, 2008)
  3. ^ "Striking a balance". Dave Christie, AMD Developer blogs. May 7, 2009. Retrieved 2009-05-08.
  4. ^ "128-Bit SSE5 Instruction Set". AMD Developer Central. Retrieved 2008-01-28.
  5. ^ "Intel Advanced Vector Extensions Programming Reference" (PDF). Intel. Retrieved 2008-04-05.
  6. ^ "Intel Advanced Vector Extensions Programming Reference". Intel. Retrieved 2009-05-06.
  7. ^ "Striking a balance". Dave Christie, AMD Developer blogs. May 7, 2009. Retrieved 2009-05-08.
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