BiCMOS
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In integrated circuit technologies, BiCMOS, also called BiMOS, refers to the integration of bipolar junction transistors and CMOS technology into a single device. This technology has commercial application in amplifier and discrete component logic design. More recently it has become the technology of choice for power electronics products[citation needed] such as voltage regulators.
History
Historically, integrating bipolar and metal–oxide–semiconductor (MOS) transistors into a single device proved difficult and uneconomical. So until now most integrated circuits have used one or the other, according to application requirements. Bipolar transistors offer high speed, high[citation needed] gain, and low output resistance, whereas CMOS technology offers high input resistance, which translates to simple, low-power logic gates. For years designers of circuits utilizing discrete components have realized the advantages of integrating the two technologies; however, lacking implementation in integrated circuits, application was restricted to fairly simple designs.
In the 1990s[citation needed], modern integrated circuit (IC) fabrication technologies began to make BiCMOS a reality. This technology rapidly found application in amplifiers and analog power management circuits, and has some advantages in digital logic. BiCMOS circuits use the characteristics of each type of transistor most appropriately. Generally this means that high current circuits use metal–oxide–semiconductor field-effect transistor (MOSFETs) for efficient control, and portions of specialized very high performance circuits use bipolar devices. Examples of this include radio frequency (RF) oscillators, bandgap-based references and low noise circuits. The Pentium, Pentium Pro, and SuperSPARC microprocessors also used BiCMOS[citation needed].
BiCMOS Process Flow
We start up with a lightly-doped P-type wafer and form the buried N+ layer by ion implantation of antimony into the respective mask pattern. The pattern is etched in a 50nm thick oxide covering the substrate. The structure before the antimony implantation is shown in Figure 5.2-1. Afterwards, a high temperature anneal is performed to remove damage defects and to diffuse the antimony into the substrate. During this anneal an oxide is grown in the buried N+ windows to provide a silicon step for alignment of subsequent levels. To achieve breakdown between the buried N+ regions a self-aligned punchtrough implant is performed. Therefore, the nitride mask is selectively removed and the remaining oxide serves as blocking mask for the buried P-layer implant (see Fig. 5.2-2).
Figure 5.2-1: Device cross-section of BiCMOS process showing N+ buried layer implant.
Figure 5.2-2: Device cross-section of BiCMOS process showing P buried layer self aligned implant
After removing all oxide a thick epitaxial layer with intrinsic doping is grown on top (see Fig. 5.2-3). After the buried layer alignment is finished, a twin well process is used to fabricate the N-well of the PMOS and the collector of the NPN device. Therefore, the same masks are used as for the buried layers. Again, the wafer is capped with a nitride layer which is opened at the N+ regions. After implanting the N-type dopant a 350nm thick oxide is grown and the nitride is stripped from the P+ regions. The subsequent P-well implant is self-aligned to the well edge (see Fig. 5.2-5). As compared to conventional CMOS a relatively short well drive-in (200min) is performed at with the oxide cap in place.
Figure 5.2-3: Device cross-section of BiCMOS process after growth of the EPI-layer.
Figure 5.2-4: Device cross-section of BiCMOS process showing EPI-layer masking for N-well implant.
Figure 5.2-5: Device cross-section of BiCMOS process showing self-aligned P-well implant.
Previously, the N-wells were implanted and a 350nm oxide is grown, which serves as blocking mask for the P-well implant. After the wells are fabricated the whole wafer is planarized and a pad oxide is grown. The oxide is capped with a thick nitride. After patterning the active regions of the device, an etch step is used to open up the field isolation regions. Prior to field oxidation, a blanket channel stop is implanted (see Fig. 5.2-6).
Figure 5.2-6: Device cross-section of BiCMOS process showing channel stop implant. Before, the wafer was planarized and patterned.
Oxidation is used to fabricate a 850nm thick field oxide. To minimize buried layer diffusion the oxidation temperature is quite moderate ( ). After removal of the nitride masks from the active regions the structure is patterned to implant the deep N+ subcollector. Therefore, phosphorus is implanted into the N-well of the collector region (see Fig. 5.2-7).
Figure 5.2-7: Device cross-section of BiCMOS process showing deep N+ subcollector implant. The PMOS and NMOS devices are protected by the photoresist.
We continue with the fabrication of the intrinsic base for the bipolar device. Therefore, the base region is opened and the base implant is performed. To ensure low base-emitter capacitance a thicker gate oxide is deposited after the base implant. This oxide will also serve as implantation shelter for the base region caused from the CMOS threshold implants. The deposited oxide has to be removed from the non base regions by an etch step. The structure after the intrinsic base implant and prior to the base oxide deposition is shown in Figure 5.2-8.
Figure 5.2-8: Device cross-section of BiCMOS process showing the intrinsic base implant.
Figure 5.2-9: Device cross-section of BiCMOS process showing the fabrication of the polysilicon emitter. The emitter window is opened, followed by the polysilicon deposition. The polysilicon is implanted and will serve as outdiffusion source to form the emitter junction.
We proceed with the resist strip and perform a pre-gate oxide etch to clean the oxide surface. A 20nm thick gate oxide is grown on top. The active emitter window is patterned and opened up with an etching process until the whole gate oxide is removed in the emitter region. Then a polysilicon layer is deposited, which forms the emitter contact as well as the gate polysilicon layers. This polysilicon layer is implanted with arsenic which will diffuse out from the polysilicon layer at the final source-drain anneal to form the emitter junction (see Fig. 5.2-9).
Figure 5.2-10: Device cross-section of BiCMOS process before the NMOS LDD doping is implanted. The subcollector is opened to collect additional N-type doping.
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Figure 5.2-11: Device cross-section of BiCMOS process showing the source-drain implantation of the NMOS device. Again, phosphorus is implanted into the subcollector region.
The polysilicon layer is patterned to define the CMOS gates and the bipolar emitter. After emitter formation, all subsequent process steps are well known from CMOS technology. Phosphorus is implanted to form a shallow LDD region for the NMOS device (see Fig 5.2-10). Then the sidewall spacer formation is initiated. Therefore, an oxide layer is deposited and anisotropically etched back. Next, the source-drain regions are heavily doped by phosphorus and boron, which is depicted in Figure 5.2-11 and Figure 5.2-12, respectively. The P+ source-drain implant is also used for the extrinsic base fabrication.
Finally, the fabrication of the active regions is finished by the source-drain anneal, which is optimized for outdiffusion conditions of the bipolar device. Hence, a 15s long RTA anneal at is performed. The final device structure including the active area dopings is shown in Figure 5.2-13.
Figure 5.2-12: Device cross-section of BiCMOS process showing the PMOS source-drain implantation, which is also applied to the base to form the extrinsic base doping.
Figure 5.2-13: Device cross-section of BiCMOS process after fabrication of the active areas. The source-drain anneal is optimized to emitter outdiffusion conditions. Afterwards the structure is scheduled for a double-level interconnect process.
Advantages
MOS circuits are ideally suited for use in logic (digital) applications because of their low current consumption. Bipolar devices are critical for creating accurate voltage references and when very low noise is required. Since the early 1990s power MOS devices (power FETs) are also used extensively in BiCMOS ICs for switching or regulating high currents as this can be done easily with low complexity control circuits. The major mixed-signal semiconductor suppliers all have power BiMOS processes for these applications. Freescale's SMARTMOS process is an example of a commercially successful BiCMOS process which uses the characteristics of the different transistors very effectively. Other companies' BiCMOS process include Texas Instruments' LBC process, Maxim's BCDMOS, and STMicroelectronics's Bipolar-CMOS-DMOS (BCD) technology[1].
Difficulties
BiCMOS as a fabrication process is not currently as commercially viable for some applications such as microprocessors as either BJT or CMOS fabrication. Unfortunately, many of the improvements to CMOS fabrication, for example, do not transfer directly to BiCMOS fabrication. An inherent difficulty arises from the fact that fine tuning of both the BJT and MOS components is impossible without adding many extra fabrication steps, and consequently increasing the cost. Finally, in the area of high performance logic, BiCMOS may never offer the (relatively) low power consumption of CMOS alone.