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Talk:OpenRISC 1200

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This is an old revision of this page, as edited by Jeremybennett (talk | contribs) at 20:08, 24 October 2011 (→‎Performance). The present address (URL) is a permanent link to this revision, which may differ significantly from the current revision.

Performance

I'm not sure the performance figures are at all helpful, and in the absence of a citation, I find them very hard to believe. The OpenRISC typically runs on FPGA's clocked at 25-50MHz, although the latest FPGAs can wind that up closer to 100MHz. There are known issues with the implementation of the caches and MMUs that constrain performance. Jeremybennett (talk) 19:53, 24 October 2011 (UTC)[reply]

Following discussion with various OpenCores contributors, no one seems to believe these are credible performance data. In the absence of a citation, I propose removing them (and possibly replacing them with substantiated data). Jeremybennett (talk) 20:08, 24 October 2011 (UTC)[reply]

History

The history section was wrong, reflecting a confusion between the OpenRISC 1000 (which is an architectural specification for a family of processors) and the OpenRISC 1200 which was the first implementation of that architecture. Text corrected. Jeremybennett (talk) 19:49, 24 October 2011 (UTC)[reply]