Control/Status Register
Control and Status Register (CSR) is a register in many central processing units that are used as storage devices for information about instructions received from machines. The device is generally placed in the register address 0 or 1 in CPUs [1] and works on the concept of using a comparison of flags (carry, overflow and zero, usually) to decide on various If-then instructions related to electronic decision flows [2][3][4]
References
- ^ http://www.pa.msu.edu/hep/d0/ftp/l1/framework/hardware/general/fpga_registers.txt
- ^ http://encyclopedia2.thefreedictionary.com/Control+and+Status+Register
- ^ https://docs.google.com/gview?a=v&q=cache:_L5LZzjO5ZgJ:web.mit.edu/course/6/6.375/install/Bluespec-2009.03.beta1/training/BSV/tutorials/configbus/tutorial-configbus.pdf+%22Control+Status+Register%22+definition+site:mit.edu&hl=en&gl=in&pid=bl&srcid=ADGEESjgQrPdjrcxGxMRwAUpYkGqpnzO-dW2KV0XQKInHE1nz5IOkux9SvmzcY-aBEobiuBQ4hyXTruwteZKXU9PMe69QZCIOVlxCzrx6zMPojKlxCQ1R7eWGBgGZnsqnPyWTZd16oOA&sig=AFQjCNFFTbYfqychVSKZ5qT7d5Dzq5z7mg
- ^ http://web.mit.edu/course/6/6.375/install/Bluespec-2009.03.beta1/training/BSV/tutorials/configbus/tutorial-configbus.pdf