Digital clock manager
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- Multipling or dividing an incoming clock (DFS).
- Reconditioning a clock for a steady duty cycle duty cycle.
- Adding a phase shift using a Delay-locked loop
- Eliminating clock skew within an FPGA design.
- "Using Digital Clock Managers (DCMs) in Spartan-3 FPGAs" (PDF). 070804 xilinx.com
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