Extended superframe

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In telecommunications, extended superframe (ESF) is a T1 framing standard.

ESF is sometimes called D5 Framing because it was first used in the D5 channel bank, invented in the 1980s.

It is preferred to its predecessor, superframe, because it includes a cyclic redundancy check (CRC) and 4000 bit/s channel capacity for a data link channel (used to pass out-of-band data between equipment.) It requires less frequent synchronization than the earlier superframe format, and provides on-line, real-time monitoring of circuit capability and operating condition.

An extended superframe is 24 frames long, and the framing bit of each frame is used in the following manner:

  • All odd-numbered frames (1, 3, ..., 23) are used for the data link (totalling 4000 bits per second),
  • Frames 2, 6, 10, 14, 18, and 22 are used to pass the CRC total of the previous extended superframe (all 4632 bits, framing and data), and
  • Frames 4, 8, 12, 16, 20, and 24 are used to send the fixed framing pattern, 001011.

The CRC is computed using the polynomial x6+x+1 over all 24×193 = 4632 bits (framing and data) of the previous superframe, but with its CRC bits forced to 1 for the purpose of CRC computation.[1] The purpose of this small CRC is not to take any immediate action, but to keep statistics on the performance of the link.

Like the predecessor superframe, every sixth frame's least-significant data bit can be used for robbed-bit signaling of call supervision state. However, there are four such bits (ABCD) per channel per extended superframe, rather than the two bits (AB) provided per superframe. (Specifically, the robbed bits follow framing bits 6, 12, 18 and 24.)

Unlike the superframe, it is possible to avoid robbed-bit signalling and send call supervision over the data link instead.

References

  • Public Domain This article incorporates public domain material from Federal Standard 1037C. General Services Administration. Archived from the original on 2022-01-22.
  1. ^ Yoon, Hee Byung (June 1991). The Error Performance Analysis Over Cyclic Redundancy Check Codes (PDF) (M.Sc. thesis). Naval Postgraduate School. pp. 8–10.