File talk:4004 dil.svg
Where read and write signals to RAM?
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As I understand CR-RAM0, CR-RAM1, CR-RAM2, CR-RAM3 is address to 1 of 16 RAM registers. But one bit CPU is impossible so there is 4 bits written to 1 of 16 RAM registers per instruction. It is very important to understand, address for example 1011 (CR-RAM0, CR-RAM1, CR-RAM2, CR-RAM3) can write one bit (0 or 1) to RAM or read one bit from RAM. But one bit computer is impossible, which in each operation would write or read 1 bit to or from RAM. So simply 4 inputs there is D0, D1, D2 and D3. So technicly it even impossible to save one bit in RAM, you must save 4 bits. So you have 4 wires (D0, D1, D2 and D3) and write or read signal should be and for example 1011 will be written to 1 of 16 addresses CR-RAM0, CR-RAM1, CR-RAM2, CR-RAM3 as 4 bits, instead that you have 16 RAM registers, which can address 1 bit with address by CR-RAM0, CR-RAM1, CR-RAM2, CR-RAM3. So 4 bits (for example, value 1100) are written instantly to the same address 1011. So thats why minimum number of bits can be written or read from RAM is 1 byte (8 bits on modern CPUs). So from here don't hard to see, that for modern 64 bits [DDR] RAM bus need 64+64+1+1=130 wires (131 wire if count GND as Ground or minus); 64 bits for RAM address, 64 bits for data per cycle and 1 bit for write signal and 1 bit for read signal. Thats why 32 bit CPU can address 2^32 = 4 GB of RAM, because minimum addressing count of information is 8 bits. So on diagram I don't see nor read nor write pin of 4004 to 4002 (RAM). And theoreticly you can't access more memory than 16*4=64 bits (compare to what written about 320 bits on page 4 about 4002. Of course maybe you can do this, but it will be 320/64=5 times slower (who would want such slow memory access?). Or if you want to access 320 bits instead 64 bits, but fast like writing to 64 bits RAM, then there must be additional 2 or 3 wires for 2^2 * 64=256 bits RAM or 2^3 *64= 512 bits RAM respectivly. In most optimistic scenario there 320 bit of RAM can be accessed like said in manual page 4 about 4002, that 4bits are written serial into 20 chanks to called some "registres" (perhaps 4 4002); this would mean, that you can't access each 4bits cell, but can access in worst case 4 register of 80 bits wide each and to store only 4 80 bits numbers or 4 instructions (each instruction from 4 bits to 80 bits long). In best case 4004 can access 16 registers each of 20 bits (but can't put shorter number or instruction than 20 bits), if assume that RAM is of 320 bits. So short instruction of 4 bits is 5 times longer; instructions of 8 bits is 20/8=2.5 time longer; 20 bits instructions or something storing of 20 bits is at the same speed as to 64 bits RAM.
My wildest guess about DDR (2xFrequency) and GDDR (4xFrequency) is that CPU can write to memory 2 or 4 times respectivly and read (but not from the same address and not write to the address already used). Or those are fake or maybe even all memory already working on CPU frequency and there's no cashes. Why would someone create cashes if simply 10 times less RAM would work at same frequency like cache? And there no programs RAM's hungry.
