Gajski-Kuhn chart

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The Gajski-Kuhn chart (or Y diagram) depicts the different perspectives in VLSI hardware design.[1] Mostly, it is used for the development of integrated circuits. Daniel Gajski and Robert Kuhn developed it in 1983. In 1985, Robert Walker and Donald Thomas refined it.

According to this model, the development of hardware is perceived within three domains that are depicted as three axis and produce a Y. Along these axis, the abstraction levels that describe the degree of abstraction. The outer shells are generalisations, the inner ones refinements of the same subject.

The issue in hardware development is most often a top-down design problem. This is perceived by the three domains of behaviour, structure, and the layout that goes top-down to more detailed abstraction levels. The designer can select one of the perspectives and then switch from one view to another. Generally, the design process is not following a specific sequence in this diagram.

  • On the system level, basic properties of an electronic system are determined. For the behavioural description, block diagrams are used by making abstractions of signals and their time response. Blocks used in the structure domain are CPUs, memory chip, etc.
  • The algorithmic level is defined by the definition of concurrent algorithms (signals, loops, variables, assignments). In the structural domain, blocks like ALUs are in use.
  • The register-transfer level (RTL) is a more detailed abstraction level on which the behaviour between communicating registers and logic units is described. Here, data structures and data flows are defined. In the geometric view, the design step of the floorplan is located.
  • The logical level is described in the behaviour perspective by boolean equations. In the structural view, this is displayed with gates and flip-flops. In the geometric domain, the logical level is described by standard cells.
  • The behaviour of the circuit level is described by mathematics using differential equations or logical equations. This corresponds to transistors and capacitors up to crystal lattices.


  1. ^ Grout, Ian (2008). Digital Systems Design with FPGAs and CPLDs. Butterworth Heinemann. p. 724. ISBN 075068397X. 

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