Jump to content

VerilogCSP

Edit links
From Wikipedia, the free encyclopedia

This is an old revision of this page, as edited by GreenC bot (talk | contribs) at 18:27, 8 September 2016 (WaybackMedic 2). The present address (URL) is a permanent link to this revision, which may differ significantly from the current revision.

In integrated circuit design, VerilogCSP [1] is a set of macros added to Verilog HDL to support Communicating Sequential Processes (CSP) channel communications. These macros are intended to be used in designing digital asynchronous circuits. VerilogCSP also describes nonlinear pipelines and high-level channel timing properties, such as forward and backward latencies, minimum cycle time, and slack.

References

  1. ^ Saifhashemi, Arash; Peter Beerel. "High Level Modeling of Channel-Based Asynchronous Circuits Using Verilog". CPA 2005.
Retrieved from "https://en.wikipedia.org/w/index.php?title=VerilogCSP&oldid=738396905"