Globally asynchronous locally synchronous
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Globally asynchronous locally synchronous (GALS) is a Model of Computation (MoC) that emerged in the 80s. It is based on the Synchronous programming and on the Asynchronous programming. It allows to relax the synchrony assumption to model and design computer systems consisting of several so-called synchronous islands (the program of each such island obeying the synchronous programming) interacting with each other with asynchronous communication, e.g., FIFOs.
A GALS circuit consists of a set of locally synchronous modules communicating with each other via asynchronous wrappers. Each synchronous subsystem ("clock domain") can run on its own independent clock (frequency). Advantages include much lower electromagnetic interference (EMI). The CMOS circuit (logic gates) requires relatively large supply current when changing state from 0 to 1. These changes are aggregated for synchronous circuit as most changes are initialised by an active clock edge. Therefore large spikes on supply current occur at active clock edges. These spikes can cause large electromagnetic interference, and may lead to circuit malfunction. In order to limit these spikes large number of decoupling capacitors are used. Another solution is to use a GALS design style, i.e. design (locally) is synchronous (thus easer to be designed than asynchronous circuit) but globally asynchronous, i.e. there are different (e.g. phase shifted, rising and falling active edge) clock signal regimes thus supply current spikes do not aggregate at the same time. Consequently GALS design style is often used in system-on-a-chip (SoC). 
- Synchronous programming
- Asynchronous programming
- Concurrency (computer science)
- Asynchronous circuit
- Asynchronous system
- clock domain crossing
- SIGNAL (a dataflow-oriented synchronous language enabling multi-clock and GALS specifications)
- Zhoukun WANG and Omar HAMMAMI. "A 24 Processors System on Chip FPGA Design with Network on Chip". 
- "A Deterministic Globally Asynchronous Locally Synchronous Microprocessor Architecture". CiteSeerX: 10
.1 .1 .91 .9608.
- Dataflow Architectures for GALS
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