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In an ideal synchronous circuit, every change in the logical levels of its storage components is simultaneous. These transitions follow the level of change of a special signal called as the clock. Ideally, the input to each storage element has reached its final value before the next clock occurs, so the behaviour of the whole circuit can be predicted exactly. Practically, some delay is required for each logical operation, resulting in a maximum speed at which each synchronous system can run.
To make these circuits work correctly, a great deal of care is needed in the design of the Clock Distribution Networks. Static timing analysis is often used to determine the maximum safe operating speed.
Nearly all digital circuits, and in particular nearly all CPUs, are fully synchronous circuits with a global clock. Exceptions are often compared to fully synchronous circuits. Exceptions include self-synchronous circuits, globally asynchronous locally synchronous circuits, and fully asynchronous circuits.
- Asada and Ikeda Laboratories. "Self-synchronous Circuit". "Self Synchronous FPGA". 2009.
- "self synchronous configurable logic blocks".
- Devlin, Benjamin; Ikeda, Makoto; Asada, Kunihiro. "Energy Minimum Operation with Self Synchronous Gate-Level Autonomous Power Gating and Voltage Scaling". 2012. doi:10.1587/transele.E95.C.546
- Devlin, B. ; Ueki, H. ; Mori, S. ; Miyauchi, S. ; Ikeda, M. ; Asada, K. "Performance and side-channel attack analysis of a self synchronous montgomery multiplier processing element for RSA in 40nm CMOS". 2012. doi:10.1109/ASSCC.2012.6570807
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