MOS Technology 6510
|Max. CPU clock rate||0.985 MHz to 1.023 MHz|
The primary change from the 6502 was the addition of an 8-bit general purpose I/O port (only six I/O pins were available in the most common version of the 6510). In addition, the address bus could be made tristate.
The 6510 was only widely used in the Commodore 64 home computer and its variants. In the C64 the extra pins of the processor were used to control the computer's memory map by bank switching, and in the C64 also for controlling three of the four signal lines of the Datassette tape recorder (the electric motor control, key-press sensing and write data lines; the read data line went to another I/O chip). It was possible, by writing the correct bit pattern to the processor at address $01, to completely expose almost the full 64KB of RAM in the C64, leaving no ROM or I/O hardware exposed except for the processor I/O port itself.
In 1985 MOS produced the 8500, an HMOS version of the 6510. Other than the process change, it is virtually identical to the NMOS version of the 6510. The 8500 was originally designed for use in the modernised C64, the C64C. However in 1985, limited quantities of 8500s were found on older NMOS-based C64s. It finally made its official debut in 1987, appearing in a motherboard using the new 85xx HMOS chipset.
The 7501/8501 variant of the 6510 was used in Commodore's C16, C116 and Plus/4 home computers, where its I/O port controlled not only the Datasette but also the CBM Bus interface. The 2 MHz-capable 8502 variant was used in the Commodore C128. All these CPUs are opcode compatible (including undocumented opcodes), except the 8502, where some differences concerning the undocumented opcodes have been reported[by whom?].
- MOS 6510 datasheet (GIF format, zipped)
- MOS 6510 datasheet (PDF format)
- MOS 6510 datasheet (Nov. 1982, PDF format)
- Marat Fayzullin's emulator page (includes downloadable source code for 6502)
- A web server using a MOS 6510 computer aka C64 unmodified