Open Core Protocol
||This article contains wording that promotes the subject in a subjective manner without imparting real information. (October 2009)|
The Open Core Protocol (OCP) is an openly licensed, core-centric protocol intended to meet contemporary system level integration challenges. OCP defines a bus-independent, configurable and scalable interface for on-chip subsystem communications. OCP International Partnership (OCP-IP) now offers the 2.2 version specification that further extends capabilities in areas such as very high performance multithreading, synchronization primitives and single-request/multiple-data transactions. OCP data transfer models range from simple request-grant handshaking through pipelined request-response to complex out-of-order operations.
Legacy IP cores can be adapted to OCP, while new implementations may take full advantage of advanced features: designers select only those features and signals encompassing a core’s specific data, control and test configuration. Core definition using OCP encapsulates a complete system integration description enabling core and test bench reuse without rework. Not only does OCP provide clear delineation of design responsibilities for core authors and System-on-Chip (SoC) integrators, but also institutes a key partitioning formalism for verification engineers and automation software.
The aim of the members is to establish a de facto standard which is widely supported by the industry.
- Eliminates the ongoing task of interface protocol (re)definition, verification, documentation and support
- Readily adapts to support new core capabilities
- Test bench portability simplifies (re)verification
- Limits test suite modifications for core enhancements
- Interfaces to any bus structure or on-chip network
- Delivers industry-standard flexibility and reuse
- Point-to-point protocol can directly interface two cores
- Neither Altera nor Xilinx, the two largest FPGA vendors, supports this protocol.
The OCP promotes IP core reusability and reduces design time, design risk and manufacturing costs for SoC designs. It focuses exclusively on IP core interfacing without preempting interconnect topology or other application-specific integration choices.
- Enables IP core creation to be independent of system architecture and application domain
- Describes all inter-core communications
- Optimizes die area by configuring into the OCP interface only those features needed by the core
- Specified timing categories assure core interoperability
- Facilitates rapid, plug-and-play IP integration