A status register, flag register, or condition code register is a collection of status flag bits for a processor. An example is the FLAGS register of the x86 architecture. The flags might be part of a larger register, such as a program status word (PSW) register.
The status register is a hardware register which contains information about the state of the processor. Individual bits are implicitly or explicitly read and/or written by the machine code instructions executing on the processor. The status register in a traditional processor design includes at least three central flags: Zero, Carry, and Overflow, which are set or cleared automatically as side effects of arithmetic operations. They may then be tested via conditional branch or jump instructions. Some CPU architectures, such as the MIPS and Alpha architectures, do not have dedicated arithmetic flags.
A status register may often have other fields as well, such as more specialized flags, interrupt enable bits, and similar types of information. During an interrupt, the status of the thread currently executing can be preserved (and later recalled) by storing the current value of the status register along with the program counter and other active registers into the machine stack or some other reserved area of memory.
This is a list of the most common CPU status register flags, implemented in almost all modern processors.
|Z||Zero flag||Indicates that the result of an arithmetic or logical operation (or, sometimes, a load) was zero.|
|C||Carry flag||Enables numbers larger than a single word to be added/subtracted by carrying a binary digit from a less significant word to the least significant bit of a more significant word as needed. It is also used to extend bit shifts and rotates in a similar manner on many processors (sometimes done via a dedicated X flag).|
|S / N||Sign flag
|Indicates that the result of a mathematical operation is negative. In some processors, the N and S flags are distinct with different meanings and usage: One indicates whether the last result was negative whereas the other indicates whether a subtraction or addition has taken place.|
|V / O / W||Overflow flag||Indicates that the signed result of an operation is too large to fit in the register width using twos complement representation.|
This is a partial list of other, less common status flags that various CPUs support.
|H / A||Half-carry flag
Decimal adjust flag
|Indicates that a bit carry was produced between the nibbles (typically between the 4-bit halves of a byte operand) as a result of the last arithmetic operation. Such a flag is generally useful for implementing BCD arithmetic operations on binary hardware.|
|P||Parity flag||Indicates whether the number of set bits of the last result is odd or even.|
|I||Interrupt flag||On some architectures, indicates that an interrupt is currently active, and that the currently executing code is part of an interrupt handler routine. On other architectures, indicates whether interrupts are enabled or masked.|
|S||Supervisor flag||Indicates that CPU is operating in supervisor mode, having enhanced permissions enabled and access to special instructions typically reserved for the operating system itself, as opposed to the normal "user" instruction set.|
CPU architectures without arithmetic flags
Some RISC instruction set architectures dispose of centrally located arithmetic result status bits. The reasons cited are interlocking between commands setting/accessing status flag, which either leads to performance degradation or need of extra hardware to work around problems in pipelined, superscalar, and speculative processors. MIPS, DEC Alpha, and AMD 29000 are examples of such architectures. Instead of most arithmetic/logical operations setting status flags implicitly, they provide explicit comparison instructions which store result in a general-purpose register as true/false (represented by a single bit or 0/1 integer). Conditional branches test true/false value in a general purpose register. Sometimes, compare and jump operations are combined in one instruction (e.g., compare 2 register and jump if equal).
Usually, comparison instructions provided for arithmetic equalities and inequalities. Testing other conditions like Carry or Overflow can be achieved employing equivalence formulas. For example, on MIPS, double-word (and generally, arbitrary-precision) addition can be achieved with the following assembly code:
# alow = blow + clow addu alow, blow, clow # set tmp = 1 if alow < clow, else 0 sltu tmp, alow, clow addu ahigh, bhigh, chigh addu ahigh, ahigh, tmp
"sltu" instruction is "set 1 if less then, 0 otherwise". In the code above, it effectively calculates carry flag from alow + blow addition, using following equivalence expression: result of addition should be greater-or-equal than either operand; if it is less instead, it means that (two-complements) overflow occurred, i.e. a carry out.
- Toshiba 900 Operation Manual, chap. 3
- Mashey, John (1996-06-04). "Carry bits; The Architect's Trap". Retrieved 2013-10-05.