# Thermal resistance

(Redirected from Thermal resistance in electronics)

Thermal resistance is a heat property and a measurement of a temperature difference by which an object or material resists a heat flow (heat per time unit or thermal resistance). Thermal resistance is the reciprocal of thermal conductance. In terms of insulation, the thermal resistance is measured by the R-value.

• Thermal resistance R has the units (m2K)/W in SI units or (ft2·°F·hr)/Btu in imperial units.
• Specific thermal resistance or specific thermal resistivity Rλ in (K·m)/W is a material constant.
• Absolute thermal resistance Rth in K/W is a specific property of a component. For example, Rth is a characteristic of a heat sink.

## Absolute thermal resistance

Absolute thermal resistance is the temperature difference across a structure when a unit of heat energy flows through it in unit time. It is the reciprocal of thermal conductance. The SI units of thermal resistance are kelvins per watt or the equivalent degrees Celsius per watt (the two are the same since the intervals are equal: Δ1 K = Δ1 °C).

The thermal resistance of materials is of great interest to electronic engineers because most electrical components generate heat and need to be cooled. Electronic components malfunction or fail if they overheat, and some parts routinely need measures taken in the design stage to prevent this.

## Analogies

Main article: hydraulic analogy

Electronic engineers are familiar with Ohm's law and so often use it as an analogy when doing calculations involving thermal resistance. Mechanical engineers are more familiar with Hooke's law and so often use it as an analogy when doing calculations involving thermal resistance.

type structural analogy[1] hydraulic analogy thermal electrical analogy[2]
quantity ... $...$ [...] m3 of water heat $Q$ [J] charge $q$ [C]
potential displacement $X$ [m] pressure $P$ [N/m2] temperature $T$ [K=J/$k_B$] potential $V$ [V=J/C]
flux load or force $F$ [N] flow rate $Q$ [m3/s] heat transfer rate $\dot{Q}$ [W=J/s] current $I$ [A=C/s]
flux density stress $\sigma$ [N/m2 = Pa] velocity [m/s] heat flux $\overrightarrow{q}$ [W/m2] current density $j$ [C/(m2·s) = A/m2]
resistance flexibility $1/k$ [...] fluid resistance $R$ [...] thermal resistance $R$ [...] electrical resistance $R$ [Ω]
conductivity stiffness $k$ [N/m] thermal conductivity$1/R$ [W/(K·m)] electrical conductance $1/R$ [...]
lumped element linear model Hooke's law $\Delta X = F/k$ Hagen–Poiseuille equation $\Delta P = Q R$ Newton's law of cooling $\Delta T = \dot{Q} R$ Ohm's law $\Delta V = IR$
distributed linear model ... $...$ Fourier's law $\overrightarrow{q} = - k {\nabla} T$ Ohm's law $\mathbf{J} = \sigma \mathbf{E}$

### Explanation from an electronics point of view

#### Equivalent thermal circuits

The diagram shows an equivalent thermal circuit for a semiconductor device with a heat sink:
$Q$ is the power dissipated by the device.
$T_J$ is the junction temperature in the device.
$T_C$ is the temperature at its case.
$T_H$ is the temperature where the heat sink is attached.
$T_{AMB}$ is the ambient air temperature.
$R_{\theta JC}$ is the device's absolute thermal resistance from junction to case.
$R_{\theta CH}$ is the absolute thermal resistance from the case to the heatsink.
$R_{\theta HA}$ is the absolute thermal resistance of the heat sink.

The heat flow can be modelled by analogy to an electrical circuit where heat flow is represented by current, temperatures are represented by voltages, heat sources are represented by constant current sources, absolute thermal resistances are represented by resistors and thermal capacitances by capacitors.

The diagram shows an equivalent thermal circuit for a semiconductor device with a heat sink.

#### Example calculation

Consider a component such as a silicon transistor that is bolted to the metal frame of a piece of equipment. The transistor's manufacturer will specify parameters in the datasheet called the absolute thermal resistance from junction to case (symbol: $R_{\theta JC}$), and the maximum allowable temperature of the semiconductor junction (symbol: $T_{JMAX}$). The specification for the design should include a maximum temperature at which the circuit should function correctly. Finally, the designer should consider how the heat from the transistor will escape to the environment: this might be by convection into the air, with or without the aid of a heat sink, or by conduction through the printed circuit board. For simplicity, let us assume that the designer decides to bolt the transistor to a metal surface (or heat sink) that is guaranteed to be less than $\Delta T_{HS}$ above the ambient temperature. Note: THS appears to be undefined.

Given all this information, the designer can construct a model of the heat flow from the semiconductor junction, where the heat is generated, to the outside world. In our example, the heat has to flow from the junction to the case of the transistor, then from the case to the metalwork. We do not need to consider where the heat goes after that, because we are told that the metalwork will conduct heat fast enough to keep the temperature less than $\Delta T_{HS}$ above ambient: this is all we need to know.

Suppose the engineer wishes to know how much power he can put into the transistor before it overheats. The calculations are as follows.

Total absolute thermal resistance from junction to ambient = $R_{\theta JC}+R_{\theta B}$

where $R_{\theta B}$ is the absolute thermal resistance of the bond between the transistor's case and the metalwork. This figure depends on the nature of the bond - for example, a thermal bonding pad or thermal transfer grease might be used to reduce the absolute thermal resistance.

Maximum temperature drop from junction to ambient = $T_{JMAX}-(T_{AMB}+\Delta T_{HS})$.

We use the general principle that the temperature drop $\Delta T$ across a given absolute thermal resistance $R_{\theta}$ with a given heat flow $Q$ through it is:

$\Delta T = Q \times R_{\theta}\,$.

Substituting our own symbols into this formula gives:

$T_{JMAX}-(T_{AMB}+\Delta T_{HS})=Q_{MAX} \times (R_{\theta JC}+R_{\theta B}+R_{\theta HA})\,$,

and, rearranging,

$Q_{MAX} = { { T_{JMAX}-(T_{AMB}+\Delta T_{HS}) } \over { R_{\theta JC}+R_{\theta B}+R_{\theta HA} } }$

The designer now knows $Q_{MAX}$, the maximum power that the transistor can be allowed to dissipate, so he can design the circuit to limit the temperature of the transistor to a safe level.

Let us substitute some sample numbers:

$T_{JMAX} = 125 \ ^{\circ}\mbox{C}$ (typical for a silicon transistor)
$T_{AMB} = 21 \ ^{\circ}\mbox{C}$ (a typical specification for commercial equipment)
$R_{\theta JC} = 1.5 \ ^{\circ}\mathrm{C}/\mathrm{W} \,$ (for a typical TO-220 package[citation needed])
$R_{\theta B} = 0.1 \ ^{\circ}\mathrm{C}/\mathrm{W} \,$ (a typical value for an elastomer heat-transfer pad for a TO-220 package[citation needed])
$R_{\theta HA} = 4 \ ^{\circ}\mathrm{C}/\mathrm{W} \,$ (a typical value for a heatsink for a TO-220 package[citation needed])

The result is then:

$Q = {{125-(21)} \over {1.5+0.1+4}} = 18.6 \ \mathrm{W}$

This means that the transistor can dissipate about 18 watts before it overheats. A cautious designer would operate the transistor at a lower power level to increase its reliability.

This method can be generalised to include any number of layers of heat-conducting materials, simply by adding together the absolute thermal resistances of the layers and the temperature drops across the layers.

### Derived from Fourier's Law for heat conduction

From Fourier's Law for heat conduction, the following equation can be derived, and is valid as long as all of the parameters (x and k) are constant throughout the sample.

$R_{\theta} = \frac{x}{A \times k}$

where:

• $R_{\theta}$ is the absolute thermal resistance (across the length of the material) (K/W)
• x is the length of the material (measured on a path parallel to the heat flow) (m)
• k is the thermal conductivity of the material (W/(K·m))
• A is the cross-sectional area (perpendicular to the path of heat flow) (m2)

### Problems with electrical resistance analogy

A 2008 review paper written by Phillips researcher Clemens J. M. Lasance notes that: "Although there is an analogy between heat flow by conduction (Fourier’s law) and the flow of an electrical current (Ohm’s law), the corresponding physical properties of thermal conductivity and electrical conductivity conspire to make the behavior of heat flow quite unlike the flow of electricity in normal situations. [...] Unfortunately, although the electrical and thermal differential equations are analogous, it is erroneous to conclude that there is any practical analogy between electrical and thermal resistance. This is because a material that is considered an insulator in electrical terms is about 20 orders of magnitude less conductive than a material that is considered a conductor, while, in thermal terms, the difference between an “insulator” and a “conductor” is only about three orders of magnitude. The entire range of thermal conductivity is then equivalent to the difference in electrical conductivity of high-doped and low-doped silicon."[3]

## Measurement standards

The junction-to-air thermal resistance can vary greatly depending on the ambient conditions.[4] (A more sophisticated way of expressing the same fact is saying that junction-to-ambient thermal resistance is not Boundary-Condition Independent (BCI).[3]) JEDEC has a standard (number JESD51-2) for measuring the junction-to-air thermal resistance of electronics packages under natural convection and another standard (number JESD51-6) for measurement under forced convection.

A JEDEC standard for measuring the junction-to-board thermal resistance (relevant for surface-mount technology) has been published as JESD51-8.[5]

A JEDEC standard for measuring the junction-to-case thermal resistance (JESD51-14) is relatively newcomer, having been published in late 2010; it concerns only packages having a single heat flow and an exposed cooling surface.[6][7][8]

## References

1. ^ Tony Abbey. "Using FEA for Thermal Analysis". Desktop Engineering magazine. 2014 June. p. 32.
2. ^
3. ^ a b Lasance, C. J. M. (2008). "Ten Years of Boundary-Condition- Independent Compact Thermal Modeling of Electronic Parts: A Review". Heat Transfer Engineering 29 (2): 149. doi:10.1080/01457630701673188. edit
4. ^ Ho-Ming Tong; Yi-Shao Lai; C.P. Wong (2013). Advanced Flip Chip Packaging. Springer Science & Business Media. pp. 460–461. ISBN 978-1-4419-5768-9.
5. ^ Younes Shabany (2011). Heat Transfer: Thermal Management of Electronics. CRC Press. p. 111-113. ISBN 978-1-4398-1468-0.
6. ^ Clemens J.M. Lasance; András Poppe (2013). Thermal Management for LED Applications. Springer Science & Business Media. p. 247. ISBN 978-1-4614-5091-7.
7. ^ http://www.electronics-cooling.com/2013/02/experiment-vs-simulation-part-3-jesd51-14/
8. ^ Schweitzer, D.; Pape, H.; Chen, L.; Kutscherauer, R.; Walder, M. (2011). "Transient dual interface measurement — A new JEDEC standard for the measurement of the junction-to-case thermal resistance". 2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium. p. 222. doi:10.1109/STHERM.2011.5767204. ISBN 978-1-61284-740-5. edit