Zilog Z280

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The Z280 in a PLCC68 package

The Zilog Z280 was a 16-bit microprocessor, an enhancement of the Zilog Z80 architecture, introduced in July 1987. It was basically the Z800, renamed, with slight improvements such as being fabricated in CMOS.[1] It was a commercial failure. Zilog added a memory management unit (MMU) to expand the addressing range to 16 MB, features for multitasking and multiprocessor and coprocessor configurations, a 256 byte cache, and a huge number of new instructions and addressing modes (giving a total of over 2000 combinations). Its internal clock signal can be configured to run at 1, 2 or 4 times the external clock's speed (e.g. a 12MHz CPU with a 3 MHz bus). More successful extensions of the Z80-architecture include Hitachi HD64180 in 1986 and Zilog eZ80 in 2001, among others. See further Zilog Z800.

The Z280 had many advanced features for its time, most of them never seen again on a Zilog processor:

  • Built-in instruction/data cache
  • Pipelining
  • high performance 16 bit Z-BUS interface or 8-bit Z80-compatible bus interface
  • four on-chip 16 bit counter/timers
  • four on-chip DMA channels
  • On-chip full duplex UART
  • Built-in MMU with Memory protection
  • User I/O trap
  • Supervisor mode (privileged instructions)
  • Illegal instruction trap
  • Coprocessor emulation trap
  • Burst memory access
  • Multiprocessor support, with many bus configuration modes
  • Support for multiple external coprocessors through an accelerated communication interface
  • Multiple I/O pages, which also allows for internal I/O devices without restricting the address range of the I/O ports like on eZ80, or conflicting with existing motherboard devices, like the Z180.
  • Stack overflow warning

Notes[edit]

  1. ^ EDN November 27,1986 p133

References[edit]

Further reading[edit]

This article is based on material taken from the Free On-line Dictionary of Computing prior to 1 November 2008 and incorporated under the "relicensing" terms of the GFDL, version 1.3 or later.