PDP-11

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The PDP-11 was a 16-bit minicomputer sold by DEC in the late 1970s and early 1980s. The PDP-11 was a successor to DEC's PDP-8 computer in the PDP series of computers. It has several uniquely innovative features, and its simple but effective design led to it becoming one of the most imitated computers in history. The success of the PDP-11 inspired the design of a number of similar successful CPU architectures, such as the Motorola 68000, as well as DEC's successor to the PDP-11, the VAX. PDP stands for Programmable Data Processor. This designation avoids classifying the machine as a computer which was inherently subject to capital equipment budgets.

First, the PDP-11 was designed to be produced in a factory by semiskilled labor. All of the dimensions of its pieces were relatively noncritical. All parts of the computer chassis were constructed from injection-molded plastic, or bent steel rod (lighter than sheet metal). It used a push-bonded backplane. That is, the printed circuit board plugged into a backplane connector. The backplane connector had terminals that could be connected by pushing wires into them. The terminal would cut the insulation around the wire and bite into the wire to for a gas-tight (i.e. corrosion-proof, therefore reliable) connection. The connector blocks were very similar to telephone connection blocks. The case was injection-molded plastic that snapped over the steel-rod chassis.

The CPU's microcode included a debugger that directly communicated to a standard RS-232 terminal. This was inovative because the microcode is the part of the irreducible guts of the computer, a critical part of the control unit. If it doesn't work, there is no computer. The debugger provided a way to examine the computer's registers, memory and input and output devices. Thus, if the CPU worked at all, it was possible to examine and correct the computer's internal state. The built-in debugger avoided the expense and inconvenience of a switch array, which was then the typical way to enter digital data into a near-dead computer. The microcode also included a generic bootstrap, to which all DEC disk drives were compatible. The bootstrap is the tiny piece of computer program that loads the operating system or other starting software into the computer's memory from an input device.

These two innovations meant that most of the time, the computer just worked. If it did not boot from its big disk, it would boot from its floppy. If the hardware worked at all, it talked to you through a terminal in a familiar way.

The instruction set was one of the most orthogonal ever designed. This means that each operation, i.e. addition, subtraction, etc., was cleanly and precisely separated from the method to locate the operands. This property is called "orthogonality" in an allusion to linear mathematics. This made the computer much easier to program because a programmer could memorize the operations, and the methods of accessing operands. He could then predict that any access method (or, "addressing mode") would work with any operation. He did not have to learn a list of exceptions or special cases in which an operation had a special or restricted set of addressing modes. In some logical sense, the set of addressing modes provided one "basis" and the set of operations provided another. Each is instruction separated into two six-bit address modes and a four-bit op-code. All op-codes operated with any combination of address modes. There were 8 general-purpose registers numbered 0 through 7. Any register could be used for most purposes, although register 6 was elected as the stack pointer for subroutines, and register 7 was used as Program Counter.

In the most radical departure from other, earlier computers, the PDP-11 had no dedicated bus for input/output. It had only a memory bus. All input and output devices were mapped to addresses in memory. The interrupt and bus was intentionally designed to be as simple as possible, while assuring that no event in an interrupt sequence could be missed. A device would request an interrupt by asserting an input into an interrupt daisy chain. A daisy chain is a sequence of logic gates arranged in series to prioritize events. Generally the first logic gate is for the highest priority. The daisy chain order established the priority of the device. When the CPU responded, the device would place its vector (interrupt number) on the bus. The CPU would then load the status register and starting address from the vector table, and temporarily disable interrupts. The CPU would multiply the vector by a power of two (usually just 2), and then fetch a number from that address. The address would be the starting address of code to run for the interrupt. The interrupt code would then service the device, and in the process, write to the interrupting device to turn off the interrupt signal. Finally, a special RTI (return from interrupt) instruction would enable interrupts on all devices. Note that this process prevents loss of interrupts. At every stage, if the interrupt is not serviced, it remains in place, to be sensed on the next cycle. If a sequence is erroneously started, the CPU would time out, generating a spurious interrupt. The spurious interrupt would warn users of bad hardware.

[the following information is found in DEC's PDP-11 Processor Handbook]

General register addressing modes

(R is a general register, 0 to 7; (R) is the contents of that register.)

0. Register - the value is to or from a register: OPR R ; R contains operand
1. Register deferred - register is used as a memory address to read or write: OPR (R) ; R contains address
2. Autoincrement: OPR (R)+ ; R contains address, then increment (R)
3. Autoincrement deferred: OPR @(R)+ ; R contains address of address, then increment (R) by 2
4. Autodecrement: OPR -(R) ; Decrement (R), then R contains address
5. Autodecrement deferred: OPR @-(R) ; Decrement (R) by 2, then R contains address of address
6. Index: OPR X(R) ; (R)+X is address, second word of instruction
7. Index deferred: OPR @X(R) ; (R)+X is address (second word) of address

The program counter (PC) can also be used as a general purpose register, providing the following Program Counter addressing modes:

2. Immediate: OPR #N ; Operand is contained in the instruction
3. Absolute: OPR @#A ; Absolute address is contained in the instruction
6. Relative: OPR A ; PC+4+X is address. PC+4 is updated PC
7. Relative deferred: OPR @A ; PC+4+X is address of address. PC+4 is updated PC

PDP-11 instructions

  • Single Operand instructions - one part of the word specifies the operation, referred to as "op code", the second part provides information for locating the operand.
    • CLR (clear), COM (ones complement), INC (increment), DEC (decrement), NEG (twos complement negate), TST (test), ASR (arithmetic shift right), ASL (arithmetic shift left), ROR (rotate right), ROL (rotate left), SWAB (swap bytes), ADC (add carry), SBC (subtract carry), SXT (sign extend), MFPS (move from processor status), MTPS (move to processor status)
  • Double Operand instructions - the first part of the word specifies the operation to be performed, the remaining two parts provide information for locating the operands.
    • MOV (move), ADD, SUB (subtract), ASH (shift arithmetically), ASHC (arithmetic shift combined), BIT (bit test), BIC (bit clear), BIS (bit set), XOR (exclusive OR).
  • Program Control instructions - the first part of the word specifies the operation to be performed, the second part indicates where the action is to take place in the program.
    • BR (branch unconditionally), BNE (branch if not zero), BEQ (branch if zero), BPL (branch if plus), BMI (branch if minus), BVC (branch if overflow clear), BVS (branch if overflow set), BCC (branch if carry clear), BCS (branch if carry set),
    • BGE (branch if >= 0), BLT (branch if < 0), BGT (branch if > 0), SOB (subtract one and branch if not = 0),
    • BHI (branch if higher), BLOS (branch if lower or same), BHIS (branch if higher or same), BLO (branch if lower),
  • Jump & Subroutine instructions
    • JMP (jump), JSR (jump to subroutine), RTS (return from subroutine),
    • EMT (emulator trap), TRAP, BPT (breakpoint trap), IOT (input/output trap), RTI & RTT (return from interrupt)
  • Miscellaneous instructions
    • HALT, WAIT (wait for interrupt), RESET (reset UNIBUS), MTPD (move to previous data space), MTPI (move to previous instruction space), MFPD (move from previous data space), MFPI (move from previous instruction space), MTPS (move to processor status word), MFPS (move byte from processor status word)
  • Condition Code operations
    • CLC, CLV, CLZ, CLN, CCC (clear relevant condition code), SEC, SEV, SEZ, SEN, SCC (set relevant condition code).

The four condition codes in the processor status word (PSW) are

  • N indicating a negative value
  • Z indicating a zero condition
  • V indicating an overflow condition, and
  • C indicating a carry condition.

Assembly Language Programming Example

From PDP-11 Processor Handbook: 

        ; SUBROUTINE TO OUTPUT A
        ; VARIABLE LENGTH MESSAGE
OUTPUT: MOV (R5)+,R0     ; PICK UP SA OF DATA BLOCK
        MOV (R5)+,R1     ; PICK UP NUMBER OF OUTPUTS
        NEG R1           ; NEGATE IT
AGAIN:  TSTB @#TPS       ; TEST TTO READY STATUS
        BPL AGAIN
        MOVB (R0)+,@#TPB ; OUTPUT CHARACTER
        INC R1           ; BUMP COUNTER
        BNE AGAIN
        RTS R5

Operating Systems

Several operating systems were available for the PDP-11

Clones

Several clones were also produced including:

Also see PDP-11s behind the Iron Curtain and Museum of the USSR Computers history.

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