DDR5 SDRAM: Difference between revisions
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#REDIRECT [[DDR4 SDRAM#DDR5]] {{R to section}} |
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'''DDR5 SDRAM''' is a type of Double data rate synchronous dynamic [[random-access memory]] slated for commercial release in 2018, which will support Pseudo Open Drain I/Os. It will also enable the use of Parallel Mesh Processing by non specialized applications. Parallel Mesh Processing refers to a processing technique where matrix manipulations are processed concurrently (in parallel). It is a way of partitioning, or separating data blocks in a single matrix and operating on them in parallel. This will require refinements in the way current computer memory stores data. DDR5 will be compatible with older [[DDR2 SDRAM|DDR2]], [[DDR3 SDRAM|DDR3]] and [[DDR4 SDRAM|DDR4]] standards through the use of Riser Cards as can be seen in the Dell owned US patent 13/222,938. <ref>{{cite thesis |type=Ph.D. |first=Evgenij |last=Derzapf |title=Parallel Mesh Processing |publisher=Philipps-Universität Marburg |year=2012}}</ref><ref>{{ cite patent |
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| country = US |
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| number = US 13/222,938 |
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| status = application |
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| title = Memory compatibility system and method |
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| pubdate = 2014-01-28 |
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| gdate = |
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| fdate = 2011-08-31 |
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| pridate = 2011-08-31 |
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| inventor = Stuart Allen Berke |
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| invent1 = William Sauber |
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| invent2 = |
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| assign1 = Dell Products L.P. |
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| assign2 = |
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| class = |
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}}{{Dead link|date=September 2014}}</ref><ref>{{ cite patent |
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| country = US |
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| number = U.S. Patent No. 8,493,116 |
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| status = patent |
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| title = Clock delay circuit and delay locked loop including the same. |
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| pubdate = 2013-07-23 |
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| gdate = |
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| fdate = 2011-09-14 |
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| pridate = 2010-09-15 |
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| inventor = Jong-ryun Choi |
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| invent1 = Seong-Ook Jung |
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| invent2 = Suho Kim |
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| assign1 = Samsung Electronics Co., Ltd |
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| assign2 = Industry-Academic Cooperation Foundation, Yonsei University |
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| class = |
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}}{{Dead link|date=September 2014}} |
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</ref><ref>{{Citation |
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| last = |
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| first = |
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| year = 2010-09-27 |
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| publisher = Freescale Semiconductor Datasheet Document Number MCIMX35SR2AEC |
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| title = MX35 Applications Processors for Automotive Products |
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| page = 51 |
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| url = http://www.element14.com/community/servlet/JiveServlet/downloadBody/31709-102-4-244039/Freescale-i.MX351-MCIMX351AVM4B-Learning%20Centre%20MCU-Datasheet-Freescale.Datasheet.pdf |
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| accessdate = 2014-08-06 |
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}}</ref> |
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==Reference== |
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{{reflist}} |
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== See also == |
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* [[Synchronous dynamic random access memory]] – main article for DDR memory types |
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* [[List of device bandwidths]] |
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* [[SDRAM latency]] |
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{{DRAM}} |
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[[Category:SDRAM]] |
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Revision as of 12:10, 26 November 2014
An editor has nominated this article for deletion. You are welcome to participate in the deletion discussion, which will decide whether or not to retain it. |
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