Talk:X86: Difference between revisions
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[[Special:Contributions/5.78.104.231|5.78.104.231]] ([[User talk:5.78.104.231|talk]]) 08:35, 28 August 2018 (UTC) |
[[Special:Contributions/5.78.104.231|5.78.104.231]] ([[User talk:5.78.104.231|talk]]) 08:35, 28 August 2018 (UTC) |
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{{ping|5.78.104.231}} I've no comments about your words, but would you please design or devise completely a new table rather than modifying my works? [[Special:Contributions/221.9.14.156|221.9.14.156]] ([[User talk:221.9.14.156|talk]]) 23:32, 4 September 2018 (UTC) |
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Chronology : Remove IA-64 and ARM?
In the Chronology section, I expected to see a chronology of x86 architecture. I was suprised to see that IA-64 and ARM made the list. I understand that IA-64 and ARM added either hardware or software compatibility with x86 instructions set, but wouldn't be simpler and more straightforward for readers if this chronology only tells about x86 processors only? — Preceding unsigned comment added by 174.91.223.158 (talk • contribs) 05:04, 19 June 2018 (UTC)
- I thought I would agree, but it looks like IA-64 is an important part in the evolution of x86. Not counting table entries, it looks like two paragraphs. This describes Intel's decisions along the way. As for ARM, I suppose it could do without it, but mostly it is saying that x86 isn't ARM. Gah4 (talk) 06:10, 19 June 2018 (UTC)
- No. IA-64 (Itanium) was not "part of the evolution of x86", it is a completely different architecture. Heck, the architecture design didn't even originate at Intel, but rather HP. The only relation it has to x86 was as an attempt to do things very very differently, plus support for x86 compatibility (for which performance was very poor). Intel's decisions re Itanium belong in its own article. Similar comments re ARM. They should both go. Jeh (talk) 06:13, 19 June 2018 (UTC)
- It is a failed branch of where Intel intended to go. Enough is needed for the context of those failures. Otherwise, there is no explanation for why AMD came out with AMD-64, now called x86-64, before Intel. I suspect that Intel believed that IA-64 would be built sooner, and that x86 performance would be better. The fact that it wasn't built sooner, and x86 performance was poor, is important for x86 evolution. Looking back, it is easy to see the problems, but also easy to forget them. (That is, so such mistakes don't happen again.) It needs to be here at least to explain that IA-64 isn't the Intel name for x86-64. Gah4 (talk) 15:30, 19 June 2018 (UTC)
- But does it need to be in the Chronology section? IA-64 is mentioned in x86#x86-64:
- In 2001, Intel attempted to introduce a non-x86 64-bit architecture named IA-64 in its Itanium processor, initially aiming for the high-performance computing market, hoping that it would eventually replace the 32-bit x86. While IA-64 was incompatible with x86, the Itanium processor did provide emulation capabilities for translating x86 instructions into IA-64, but this affected the performance of x86 programs so badly that it was rarely, if ever, actually useful to the users: programmers should rewrite x86 programs for the IA-64 architecture or their performance on Itanium would be orders of magnitude worse than on a true x86 processor. The market rejected the Itanium processor since it broke backward compatibility and preferred to continue using x86 chips, and very few programs were rewritten for IA-64.
- AMD decided to take another path toward 64-bit memory addressing, making sure backward compatibility would not suffer. In April 2003, AMD released the first x86 processor with 64-bit general-purpose registers, the Opteron, capable of addressing much more than 4 GB of virtual memory using the new x86-64 extension (also known as AMD64 or x64). The 64-bit extensions to the x86 architecture were enabled only in the newly introduced long mode, therefore 32-bit and 16-bit applications and operating systems could simply continue using an AMD64 processor in protected or other modes, without even the slightest sacrifice of performance and with full compatibility back to the original instructions of the 16-bit Intel 8086. The market responded positively, adopting the 64-bit AMD processors for both high-performance applications and business or home computers.
- Seeing the market rejecting the incompatible Itanium processor and Microsoft supporting AMD64, Intel had to respond and introduced its own x86-64 processor, the "Prescott" Pentium 4, in July 2004. As a result, the Itanium processor with its IA-64 instruction set is rarely used and x86, through its x86-64 incarnation, is still the dominant CPU architecture in non-embedded computers.
- so I see no reason to leave it in the chronology of x86 implementations. Guy Harris (talk) 18:20, 19 June 2018 (UTC)
- It is a failed branch of where Intel intended to go. Not where "Intel intended to go with x86". Intel is not equivalent to x86. This article is about x86, not Intel. Itanium doesn't belong in the x86 chronology table. Jeh (talk) 19:16, 19 June 2018 (UTC)
- As well as I know it, Itanium (that is, before Itanium 2) has hardware support for IA-32. That seems to be not well documented on Itanium. Starting with Itanium 2, it is software emulation only. And by the way, there are plenty of mentions of AMD and x86-64 on the Itanium page, including mentioning which OS run x86-64. (I suspect that the latter is not needed and distracting.) In the case of other processors, the table mentions them almost at the individual stepping level, but all of Itanium in one entry. As only Itanium 1 (that is, Merced) has hardware support, it seems that the entry should only cover that, along with appropriate date range. In the case of ARM, it is also describing software emulation. Gah4 (talk) 20:25, 19 June 2018 (UTC)
- If we bother to cover the Merced implementation of IA-32, we should note that this is referring only to the backwards-compatibility part of the processor, describe it as an IA-32 implementation - i.e., give the instruction set as "32-bit x86", not "IA-64" - and in "Notable features" describe only the IA-32 part of the implementation (which means removing "64-bit EPIC architecture, 128-bit VLIW instruction bundle").
- I wouldn't bother with software implementations; otherwise, we'd have to include, for example the Mac version of Virtual PC and QEMU and so on. Guy Harris (talk) 20:50, 19 June 2018 (UTC)
- The VAX-11 processors can run PDP-11 code. That doesn't mean that a table showing the chronology of PDP-11 processors should include the VAX-11. I can't think of any reason to mention software emulation - any general purpose processor can emulate any other. This table is about the chronology of x86 processors, not emulators thereof. As for other pages, that's those other pages' problems. This table isn't required to repeat their mistakes. Jeh (talk) 21:43, 19 June 2018 (UTC)
The Intel Itanium Architecture Software Developer’s Manual, revision 2.3 says
IA-32 operating system resources; IA-32 paging, MTRRs, IDT, control registers, debug registers and privileged instructions are superseded by resources defined in the Itanium architecture. All accesses to these resources result in an interception fault.
in section 6.2.1.2 "IA-32 Instruction Set Execution" when talking about the hardware IA-32 support in some Itanium processors, so Merced can't function as a full IA-32 processor, running an IA-32 operating system; all it has is the ability to run IA-32 applications under an IA-64 operating system.
This was, as I remember, also the case with the PDP-11 compatibility in the VAX, so the analogy seems complete, supporting the argument that we should not bother to mention even just Merced in the list of IA-32 generations. Guy Harris (talk) 22:25, 19 June 2018 (UTC)
@Guy Harris:, please do not be so sure about your wrong conclusion with improper documentations to reference! When in late 2004, I installed an x86 or 32-bit version of Windows Server 2003 onto one HP Itanium based server! Early Itanium based platform provided two operating environments, Itanium environment (which you mentioned and discussed on the above) and IA-32 environment. The latter is provided by the firmware rather than the O/S, it is something quite like today's CSM, which enable x86 O/S to run on EFI platform. I suggest you reference the early versions of Itanium architecture manual from Intel for related information! That is the very reason I placed the Itanium onto that table, which I have maintained for years! 221.9.13.137 (talk) 15:19, 23 June 2018 (UTC)
- So the January 2000 Intel IA-64 Architecture Software Developer's Manual, Volume 4: Itanium Processor Programmer's Guide indicates that "The Itanium processor is capable of executing IA-32 instructions in the IA-32 system environment (legacy IA-32 operating systems) provided the required platform and firmware support exists in the system."; "the Itanium processor" refers to Merced - section 1.4, "Overview of Volume 4: Itanium Processor Programmer's Guide" says "This volume describes model-specific architectural features incorporated into the Intel Itanium processor, the first IA-64 processor". That document also indicates that "When RESET# is asserted, all IA-64 processors boot in a different reset location than IA-32 processors and start executing 64-bit IA-64 of IA-32 16 bit Real Mode code.", so Merced can't be made to start up as an IA-32 processor - in order to boot an IA-32 operating system, some firmware or software would need to switch to the IA-32 system environment.
- So Itanium processors that support the IA-32 system environment (not just supporting IA-32 non-privileged code in the Itanium system environment) could perhaps be listed in the table, although the entry should only discuss the IA-32 aspects of the processor.
- The current version of the Itanium Architecture documentation speaks only of the Itanium system environment, so they've dropped the IA-32 system environment. Guy Harris (talk) 18:45, 23 June 2018 (UTC)
"Generation" column again
How did this completely unreferenced bit of stuff-someone-made-up-one-day get back in here?
This is how: https://en.wikipedia.org/w/index.php?title=X86&type=revision&diff=844673781&oldid=843473014 Another Janagewen IP sock.
It's going away. There is no reference for industry-wide "generation" numbers. Jeh (talk) 19:32, 19 July 2018 (UTC)
Fixed: Large number of problems in the chronology table
Hello.
I fixed a large number of problems in the Chronology section. Here is a detailed list of what has gotten fixed:
- Erroneous info: IA-64 and ARM64 were framed into the chronology, in a way that implied they were implementations of x86! And that's the smallest problem; this integration was so weird, it was analogous to reading an article on the life of Bill Gates that frequently strayed off the topic to explain the details of Beyonce's life in parallel. Whatever the noble motive of the original writer, the end result grossly failed to justify itself.
- Writer's pet peeves: Apparently the writer had felt the need to emphatically explain that "x64" is part of "x86". But the irony is this act would backfire because the integration of erroneous info about IA-64 and ARM64. It is like the story of the boy called wolf for the third time; when you (by mistake or intentionally) tell people that IA-64 and ARM64 are part of x86, and they find out otherwise, they don't believe you when you tell them x64 is an x86 version.
- Ambiguous info: Intel Core i3, i5 and i7 are CPU brand names, not CPU models; these brand names have been used since 2008 for the bulk of Intel products. I replaced them with the Intel CPU architecture names, e.g., Nehalem.
- Conflicting top and bottom headings:
- "Generation" ≠ "Era" (one is time, one is the product of it)
- "Introduction" ≠ "Release" (one happens once, the other can happen repeatedly afterwards)
- "Prominent CPU models" ≠ "CPU models" (not every CPU is prominent)
- "Address Space" ≠ "Physical Address Space", especially when right below the former, it says "Physical", "virtual" and "linear"
- "Notable features" ≠ "New features" (one feature can be new but not notable)
- Contested info: Please read previous discussions in this talk page
- Editorializing (e.g. "Enhanced Platform", which is zero-informative. Proof: [1])
- Broken links
- Incorrect use of slash; see MOS:SLASH
- Capitalization; see MOS:CAPS
- "NA" → "{{N/A}}"
5.78.104.231 (talk) 08:35, 28 August 2018 (UTC)
@5.78.104.231: I've no comments about your words, but would you please design or devise completely a new table rather than modifying my works? 221.9.14.156 (talk) 23:32, 4 September 2018 (UTC)