SSE2: Difference between revisions

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Revision as of 04:03, 6 November 2005

SSE2 is one of the IA-32 SIMD instruction sets, first introduced by Intel with the initial version of the Pentium 4 in 2001. It extends the earlier version SSE instruction set, and is intended to fully supplant MMX. SSE2 has itself been extended by SSE3, also known as "Prescott New Instructions", introduced by Intel to the Pentium 4 in early 2004.

Rival chip-maker AMD added support for SSE2 with the introduction of their Opteron and Athlon 64 ranges of 64-bit CPUs in 2003.

Changes

SSE2 adds support for 64-bit double-precision floating point and for 64, 32, 16 and 8-bit integer operations on the eight 128-bit XMM registers first introduced with SSE. SSE2 adds no additional program state to that provided by SSE.

The addition of 128-bit integer SIMD operations allows the programmer to completely avoid the eight 64-bit MMX registers "aliased" on the original IA-32 floating point register stack. This permits mixing integer SIMD and scalar floating point operations without mode switching required between MMX and x87 floating point operations. However, this is overshadowed by the value of being able to perform integer SIMD operations on the wider SSE registers.

Other SSE2 extensions include a set of cache-control instructions intended primarily to minimize cache pollution when processing indefinite streams of information, and a sophisticated complement of numeric format conversion instructions.

AMD's implementation of SSE2 on the AMD64 platform includes an additional 8 registers, doubling the total number to 16 (XMM0 through XMM15). These additional registers are only visible when running in 64-bit mode. Intel adopted these additional registers as part of their support for AMD64 architecture (renamed EM64T) in 2004.

CPUs which support SSE2

Notable CPUs which do not support SSE2

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 SSE2 adds support for [[IEEE floating-point standard|64-bit double-precision]] [[floating point]] and for 64, 32, 16 and 8-bit [[integer]] operations on the eight 128-bit XMM [[processor register|register]]s first introduced with SSE. SSE2 adds no additional program state to that provided by SSE.
-The addition of 128-bit integer SIMD operations allows the programmer to completely avoid the eight 64-bit MMX registers "aliased" on the original IA-32 floating point register stack.  This permits mixing integer SIMD and scalar floating point operations without mode switching required between MMX and x87 floating point operations.  However, this is overshadowed by the value of being able to perform integer SIMD operations on the wider SSE registers.
+The addition of 128-bit integer SIMD operations allows the programmer to completely avoid the eight 64-bit MMX registers "aliased" on the original IA-32 floating point register stack.  This permits mixing integer SIMD and scalar floating point operations without mode switching required between MMX and [[x87]] floating point operations.  However, this is overshadowed by the value of being able to perform integer SIMD operations on the wider SSE registers.
 Other SSE2 extensions include a set of [[CPU cache|cache]]-control instructions intended primarily to minimize cache pollution when processing indefinite streams of information, and a sophisticated complement of numeric format conversion instructions.