ARM Cortex-M

The ARM Cortex-M is a group of 32-bit RISC ARM processor cores licensed by ARM Holdings. The cores are intended for microcontroller applications, and consists of the Cortex-M0, Cortex-M0+, Cortex-M1, Cortex-M3, Cortex-M4.

ARM Cortex-M0 / Cortex-M3 ICs from NXP and Energy Micro

Overview

Main article: ARM architecture

ARM license

ARM Holdings does not manufacture nor sell CPU devices based on its own designs, but rather, licenses the processor architecture to interested parties. ARM offers a variety of licensing terms, varying in cost and deliverables. To all licensees, ARM provides an integratable hardware description of the ARM core, as well as complete software development toolset, and the right to sell manufactured silicon containing the ARM CPU.

Silicon customization

Integrated device manufacturers (IDM) receive the ARM Processor IP as synthesizable RTL (written in Verilog). In this form, they have the ability to perform architectural level optimizations and extensions. This allows the manufacturer to achieve custom design goals, such as higher clock speed, very low power consumption, instruction set extensions, optimizations for size, debug support, etc.

Instruction sets

The Cortex-M0 / M0+ / M1 implement the ARMv6-M architecture, the Cortex-M3 implements the ARMv7-M architecture, and the Cortex-M4 implements the ARMv7E-M architecture. The architectures are binary instruction upward compatible from ARMv6-M to ARMv7-M to ARMv7E-M. Binary instructions available for the Cortex-M0 / M0+ / M1 can execute without modification on the Cortex-M3 and Cortex-M4. Binary instructions available for the Cortex-M3 can execute without modification on the Cortex-M4.

All four Cortex-M cores implement a common instruction subset that consists of: Thumb subset, Thumb-2 subset, and multiply. The Cortex-M0 / M0+ / M1 include all older Thumb instructions, except new instructions (CBZ, CBNZ, IT) which were added in ARMv7-M architecture. The Cortex-M0 / M0+ / M1 include a minor subset of Thumb-2 instructions (BL, DMB, DSB, ISB, MRS, MSR).

The Cortex-M0 / M0+ / M1 were designed to be the smallest size possible, thus having the least instructions of the Cortex-M family. The Cortex-M3 adds 3 Thumb instructions and all Thumb-2 instructions, plus a 10-12 cycle hardware divide and saturated math instructions. The Cortex-M4 adds DSP instructions and an optional single-precision floating-point unit. If the Cortex-M4 has the floating point unit, then it is known as the Cortex-M4F.

ARM Cortex-M Instruction Sets

ARM Cortex-M	Thumb	Thumb-2	Hardware Multiply	Hardware Divide	Saturated Math	DSP Extensions	Floating Point	ARM Architecture
Cortex-M0	Most	Subset	1 or 32 cycle	No	No	No	No	ARMv6-M
Cortex-M0+	Most	Subset	1 or 32 cycle	No	No	No	No	ARMv6-M
Cortex-M1	Most	Subset	3 or 33 cycle	No	No	No	No	ARMv6-M
Cortex-M3	Entire	Entire	1 cycle	Yes	Yes	No	No	ARMv7-M
Cortex-M4	Entire	Entire	1 cycle	Yes	Yes	Yes	Optional	ARMv7E-M

• Note: The Cortex-M0 / M0+ / M1 doesn't include these Thumb instructions: CBZ, CBNZ, IT; nor does it include a divide instruction.
• Note: The Cortex-M0 / M0+ / M1 only include these Thumb-2 instructions: BL, DMB, DSB, ISB, MRS, MSR.
• Note: If a smaller silicon die size is required, the Cortex-M0 / M0+ / M1 can implement a smaller yet slower multiply instruction.

Optional components

The Integrated Device Manufacturers (IDM) have numerous options to configure the contents of their ARM silicon die. To determine which components have been included in an ARM IC chip, consult its datasheet and manufacturer.

• SysTick Timer. It is a 24-bit system timer that extends the functionality of both the processor and the Nested Vectored Interrupt Controller (NVIC). When present, it also provides an additional configurable priority SysTick interrupt.
• Bit Banding. It maps a complete word of memory onto a single bit in the bit-band region. For example, writing to an alias word will set or clear the corresponding bit in the bitband region. This allows every individual bit in the bit-banding region to be directly accessible from a word-aligned address, and individual bits to be toggled from C/C++ without performing a read-modify-write sequence of instructions.
• Memory Protection Unit (MPU). It provides support for protecting regions of memory through enforcing privilege and access rules. It supports up to eight different regions, each of which can be split into a further eight equal-size sub-regions.

ARM Cortex-M Optional Components

ARM Cortex-M	SysTick Timer	Bit Banding	Memory Protection Unit (MPU)
Cortex-M0	Optional	Optional	No
Cortex-M0+	Optional	Optional	Optional
Cortex-M1	Optional	No	No
Cortex-M3	Yes	Optional	Optional
Cortex-M4	Yes	Optional	Optional

• Note: Most Cortex-M3 and M4 chips have Bit-Banding and MPU. The Bit-Banding option can be added to the Cortex-M0 / M0+ using the Cortex-M System Design Kit.
• Note: Software should validate the existence of a feature before attempting to use it.

Additional components may be available

• External interrupts: 0 to 32.
• Wake-up interrupt controller: Optional.
• Vector Table Offset Register: Optional.
• Data endianness: little-endian or big-endian.
• Instruction fetch width: 16-bit only, or mostly 32-bit.
• User/Privilege support: Optional.
• Reset all registers: Optional.
• Single-cycle I/O port: Optional.
• Debug Access Port (DAP): Optional.
  • Halting debug support: Optional.
    • Number of watchpoint comparators: 0 to 2.
    • Number of breakpoint comparators: 0 to 4.

Cortex-M0

Features

Key features of the Cortex-M0 core are:

• ARMv6-M architecture
• Instruction Sets
  • Thumb (most), missing CBZ, CBNZ, IT.
  • Thumb-2 (subset), only BL, DMB, DSB, ISB, MRS, MSR.
  • 32-bit hardware multiply, 1-cycle or 32-cycles (silicon option)
• 3-stage pipeline

Implementations

The following IC vendors have developed microcontrollers based on the Cortex-M0 core:

• Energy Micro EFM32 Zero family
• NXP LPC1100 and LPC1200 families
• Nordic Semiconductor nRF51 Series RF SoC
• nuvoTon NuMicro family
• Sonix SN32F700 Series
• STMicroelectronics STM32 F0 family

Cortex-M0+

Features

Key features of the Cortex-M0+ core are:

• ARMv6-M architecture
• Instruction Sets
  • Thumb (most), missing CBZ, CBNZ, IT.
  • Thumb-2 (subset), only BL, DMB, DSB, ISB, MRS, MSR.
  • 32-bit hardware multiply, 1-cycle or 32-cycles (silicon option)
• 2-stage pipeline
• 8 region memory protection unit (MPU) (silicon option)

Implementations

The following IC vendors have licenses for the Cortex-M0+ core:

• Freescale Kinetis L Series
• NXP (future)

Cortex-M1

Features

Key features of the Cortex-M1 core are:

• ARMv6-M architecture
• Instruction Sets
  • Thumb (most), missing CBZ, CBNZ, IT.
  • Thumb-2 (subset), only BL, DMB, DSB, ISB, MRS, MSR.
  • 32-bit hardware multiply, 3-cycle or 33-cycles (silicon option)

Implementations

The following FPGA vendors support the Cortex-M1 as soft-cores:

• Actel FPGAs
• Altera FPGAs
• Xilinx FPGAs

Cortex-M3

LPCXpresso Development Board with NXP LPC1343

mbed with NXP LPC1768 microcontroller

Features

Key features of the Cortex-M3 core are:

• ARMv7-M architecture
• Instruction Sets
  • Thumb (entire)
  • Thumb-2 (entire)
  • 1-cycle 32-bit hardware multiply, 2-12 cycle 32-bit hardware divide, saturated math support
• 3-stage pipeline with branch speculation
• 1 to 240 physical interrupts, plus NMI
• 12 cycle interrupt latency
• Integrated sleep modes
• 8 region memory protection unit (MPU) (silicon option)
• 1.25 DMIPS/MHz
• 90 nm implementation
  • 32 µW/MHz
  • 0.12 mm²

Implementations

The following IC vendors have developed microcontrollers based on the Cortex-M3 core:

• Actel SmartFusion family
• Atmel SAM3 family
• Cypress Semiconductor PSoC 5
• Energy Micro EFM32 Tiny, Gecko, Leopard, Giant families
• Fujitsu FM3 family
• NXP LPC1300, LPC1700, LPC1800 families
• Silicon Labs Precision32 SiM3C1xx and SiM3U1xx families
• STMicroelectronics STM32 F2, F1, L1, W families
• Texas Instruments Stellaris, TMS470; OMAP 4470 (two Cortex-M3 coprocessors alongside the main Cortex-A9 dual-core CPU)
• Toshiba TX03 Series

Cortex-M4

Features

Conceptually the Cortex-M4 is a Cortex-M3 plus DSP Instructions, and optional floating-point unit (FPU). If a core contains an FPU, it is known as a Cortex-M4F, otherwise it is a Cortex-M4. Key features of the Cortex-M4 core are:

• ARMv7E-M architecture
• Instruction Sets
  • Thumb (entire)
  • Thumb-2 (entire)
  • 1-cycle 32-bit hardware multiply, 2-12 cycle 32-bit hardware divide, saturated math support
  • DSP extension: Single cycle 16/32-bit MAC, single cycle dual 16-bit MAC, 8/16-bit SIMD arithmetic.
  • Floating-Point extension (silicon option): Single-precision floating point unit, IEEE-754 compliant. This is called the FPv4-SP extension.
• 3-stage pipeline with branch speculation
• 1 to 240 physical interrupts, plus NMI
• 12 cycle interrupt latency
• Integrated sleep modes
• 8 region memory protection unit (MPU) (silicon option)
• 1.25 DMIPS/MHz

Implementations

The following IC vendors have developed microcontrollers based on the Cortex-M4 core:

• Atmel SAM4 family (Cortex-M4)
• Energy Micro EFM32 Wonder (Cortex-M4F)
• Freescale Kinetis families (Cortex-M4 and Cortex-M4F)
• Infineon Technologies XMC4000 family (Cortex-M4F)
• NXP Semiconductors LPC4300 family (dual core : Cortex-M4F and Cortex-M0)
• STMicroelectronics STM32 F3 and F4 families (Cortex-M4F)
• Texas Instruments Stellaris LM4F family (Cortex-M4F), OMAP 5 (two Cortex-M4 coprocessors along side the main Cortex-A15 dual-core CPU)

Development tools

Development toolchains (IDE / compiler / linker / debugger / flashing)

• TASKING VX-Toolset by Altium.
• Atmel Studio by Atmel.
• TrueSTUDIO by Atollic.
• GNU Tools for ARM Embedded Processors by Canonical.
• LPCXpresso and Red Suite by Code Red.
• Embedded Workbench for ARM by IAR.
• MDK-ARM by Keil.
• Ride and RKit for ARM by Raisonance.
• CrossWorks for ARM by Rowley.
• Sourcery CodeBench by Mentor Graphics.
• Code Composer Studio by Texas Instruments.
• YAGARTO (GNU for ARM).

Debugging tools (JTAG / SWD)

• I-jet by IAR.
• RLink Standard and RLink Professional by Raisonance.
• J-Link and J-Trace by Segger.
• JTAGjet and JTAGjet-Trace by Signum.
• ST-LINK and ST-LINK/V2 by STMicroelectronics.
• AK-LINK (OpenOCD-compatible) by Artekit.
• OpenOCD open source GDB server supports a variety of JTAG probes.

Real-Time Operating Systems (RTOS)

• BeRTOS
• ChibiOS/RT
• CoOS
• eCos
• FreeRTOS, OpenRTOS, SafeRTOS
• FunkOS
• Milos
• Nucleus
• RT-Thread
• ScmRTOS
• SDPOS
• ThreadX
• µC/OS-II, µC/OS-III
• µTasker
• Unison

C/C++ software libraries (Free)

• ARM Cortex libraries
  • Cortex Microcontroller Software Interface Standard (CMSIS)
• Alternate C standard libraries
  • dietlibc, Newlib
• FAT file system libraries
  • FatFs, Petit FatFs
• Fixed-Point math libraries
  • libfixmath

Non C/C++ computer languages

• Lua - eLua.
• Python - Python-on-a-chip.
• Java - Java evaluation kit for STM32 F2 series

Documentation

The amount of documentation for all ARM chips is daunting, especially for newcomers. The documentation for microcontrollers from past decades would easily be inclusive in a single document, but as chips have evolved so has the documentation grown. The total documentation is especially hard to grasp for all ARM chips since it consists of documents from the IC manufacturer and documents from CPU core vendor (ARM Holdings).

A typical top-down documentation tree is: high-level marketing slides, datasheet for the exact physical chip, a detailed reference manual that describes common peripherals and other aspects of physical chips within the same series, reference manual for the exact ARM core processor within the chip, reference manual for the ARM architecture of the core which includes detailed description of all instruction sets.

Documentation Tree (top to bottom)

1. IC Manufacturer Marketing Slides.
2. IC Manufacturer Datasheets.
3. IC Manufacturer Reference Manuals.
4. ARM Core Reference Manuals.
5. ARM Architecture Reference Manuals.

IC Manufacturers usually have additional documents, including: evaluation board user manuals, application notes, getting started with development software, software library documents, errata, and more.

See also

• ARM architecture, List of ARM microprocessor cores
• Microcontroller, List of common microcontrollers
• Embedded system, Single-board microcontroller
• JTAG, SWD

Further reading

• The Definitive Guide to the ARM Cortex-M0; 2nd Edition; Joseph Yiu; Newnes; 552 pages; 2011; ISBN 978-0-12-385477-3. (Online Sample)
• The Definitive Guide to the ARM Cortex-M3; 2nd Edition; Joseph Yiu; Newnes; 479 pages; 2009; ISBN 978-1-85617-963-8. (Online Sample)

External links

Official

• ARM Cortex-M Website, arm.com
• Quick Reference Cards for Instruction Sets: Thumb, ARM and Thumb-2, Vector Floating Point

Cortex-M Series	ARM Website	ARM Core	ARM Architecture
M0	M0	M0 r0p0	ARMv6-M
M0+	M0+	M0+ r0p0	ARMv6-M
M1	M1	M1 r1p0 M1 r0p1	ARMv6-M
M3	M3	M3 r2p1 M3 r2p0 M3 r1p1	ARMv7-M
M4	M4	M4 r0p1 M4 r0p0	ARMv7E-M

Other

• Migrating from ARM7TDMI to Cortex-M3, arm.com
• RISC vs. CISC in the mobile era
• Bit Banding in the STM32