Talk:Physical Address Extension: Difference between revisions

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PAE is A Processor Feature

“

Physical Address Extension (PAE) is a memory management feature for the IA-32 architecture...

”

Definitively, PAE is a processor feature, extending 32-bit instruction set to address more than 4GB Physical Memory. The quoted description is not strictly correct! In Intel document, PAE, is also used to reference to Page Address Extension mode.

“

When AMD defined their AMD64 architecture as an extension of x86, they defined an enhanced version of PAE to be used while the processor was in 64-bit mode ("long mode").

”

Not strictly correct description, it is not an enhanced version of PAE, it is an enhanced version of paging schema for this new paging schema does not apply onto the Legacy 32-bit mode operation. In other words, no 32-bit linear address mapped on the 4-level paging... CopperQA (talk) 22:55, 18 September 2015 (UTC)[reply]

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+== PAE is A Processor Feature ==
+{{cquote| Physical Address Extension (PAE) is a memory management feature for the IA-32 architecture...}}
+Definitively, PAE is a processor feature, extending 32-bit instruction set to address more than 4GB Physical Memory. The quoted description is not strictly correct! In Intel document, ''PAE'', is also used to reference to ''Page Address Extension'' mode.
+{{cquote| When AMD defined their AMD64 architecture as an extension of x86, they defined an enhanced version of PAE to be used while the processor was in 64-bit mode ("long mode"). }}
+Not strictly correct description, it is not an ''enhanced version of PAE'', it is an ''enhanced version of paging schema'' for this new paging schema does not apply onto the Legacy 32-bit mode operation. In other words, no 32-bit linear address mapped on the 4-level paging... [[User:CopperQA|CopperQA]] ([[User talk:CopperQA|talk]]) 22:55, 18 September 2015 (UTC)