Talk:Visual Instruction Set: Difference between revisions

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VIS support in SPARC64?

Poking around a little on the net, it seems like VIS is supported in at least SPARC64 VI (but maybe not earlier revs?). Can a subject expert weigh in here?--NapoliRoma 21:05, 3 December 2007 (UTC)[reply]

Found mention of VIS 1 in SPARC64 V documentation.--NapoliRoma 22:16, 3 December 2007 (UTC)[reply]

As far as I know, VIS is supported on relatively new SPARC64 processors. But some instructions are not directly supported by hardware (microcode or trap? not sure), so performance of VIS on SPARC64 might not be as good as that on UltraSPARC. Houyi 10:57, 4 December 2007 (UTC)[reply]

Other

It doesn't appear that any of the Sun external links point to anywhere except for Oracle webspam. Removing links.--thechao

The link to docs.sun.com is broken.

VIS 3.0 seems to be available in ultrasparc T3 and T4, although there is no public documentation afaict.

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Cheers.—^{cyberbot II}_{Talk to my owner:Online} 16:01, 31 March 2016 (UTC)[reply]

Differences vs x86 nonsense

Some of the comparison in the "Differences vs x86" section are nonsense.

For example:

As with the SIMD instruction set extensions on other RISC processors, VIS strictly conforms to the main principle of RISC: keep the instruction set concise and efficient.

x86 SSE vector extensions are VERY efficient and are VERY concise. They implement very general forms that suit a wide range of applications. --64.121.146.209 (talk) 13:32, 28 November 2017 (UTC)[reply]

@@ Line 27: / Line 27: @@
 Cheers.—[[User:Cyberbot II|<sup style="color:green;font-family:Courier">cyberbot II</sup>]]<small><sub style="margin-left:-14.9ex;color:green;font-family:Comic Sans MS">[[User talk:Cyberbot II|<span style="color:green">Talk to my owner</span>]]:Online</sub></small> 16:01, 31 March 2016 (UTC)
+== Differences vs x86 nonsense ==
+Some of the comparison in the "Differences vs x86" section are nonsense.
+For example:
+ As with the SIMD instruction set extensions on other [[RISC]] processors, VIS strictly conforms to the main principle of RISC: keep the instruction set concise and efficient.
+x86 SSE vector extensions are VERY efficient and are VERY concise. They implement very general forms that suit a wide range of applications. --[[Special:Contributions/64.121.146.209|64.121.146.209]] ([[User talk:64.121.146.209|talk]]) 13:32, 28 November 2017 (UTC)