Talk:Comparison of Armv8-A processors

Cavium ThunderX

• Info under: http://www.cavium.com/newsevents_Cavium_Introduces_ThunderX_A_2.5_GHz_48_Core_Family_of_Workload_Optimized_Processors_for_Next_Generation_Data_Center_and_Cloud_Applications.html
• Cavium has been known for their MIPS64-based hardware targeting networking User:ScotXW^t@lk 13:52, 6 June 2014 (UTC)

AppliedMicro X-Gene

• http://www.apm.com/products/data-center/x-gene-family/x-gene/
• Applied Micro Circuits Corporation (a.k.a. AppliedMicro or AMCC or APM) User:ScotXW^t@lk 13:54, 6 June 2014 (UTC)

Heterogeneous System Architecture

Support for ARM big.LITTLE with either In-kernel switcher (CPU migration) or Heterogeneous multi-processing (global task scheduling) is missing. Other possible HSA-features are missing. E.g. the ARM Cortex-A15 features stuff, that elder CPUs do not. More documentation on that would be nice. User:ScotXW^t@lk 18:38, 13 June 2014 (UTC)

References needed in the article

References are needed in the article. Much of the little that is there looks just made up or wrong or meaningless. Anything that does not have a justification in an article should be removed - which is the whole article at the moment.

See Comparison of ARMv7-A cores for how this should be arranged, the cores should be on the left and attributes at the top rather than the other way around as more cores will appear in the future. Even that other article is lacking in an intro and should have a reference on every line rather than just a group at the bottom. Dmcq (talk) 13:53, 19 June 2014 (UTC)

Actually...are links posted about actually references being mislocated...C933103 (talk) 14:31, 19 June 2014 (UTC)

I can't make out what you're trying to say. Dmcq (talk) 17:23, 19 June 2014 (UTC)

Interesting combo Helix - big.LITTLE?

As mixing ARMv8-A and ARMv7 could it be said to be big.LITTLE, not only heterogenous? I assume 32-bit programs could be moved between with right software, just not heard of the possibility and saying so might be WP:OR. 64-bit programs of course couldn't, and not sure if architecture, not just ISA has to be the same.. comp.arch (talk) 16:22, 9 October 2014 (UTC)

Dhrystone benchmark

There seems to be some back-and-forth about a footnote relating to the Dhrystone metric: "As Dhrystone (implied in "DMIPS") is a synthetic benchmark developed in 1980s, it is no longer representative of prevailing workloads – use with caution." To avoid an edit-war, it should probably be discussed here. The benchmark is certainly old. I would argue that comment should be in the Dhrystone article, not here. Further, perhaps the benchmark should not even be included in a table of hardware specs anyway. Dbsseven (talk) 21:28, 25 August 2016 (UTC)

As I (only) added; it's only "implied". Not all whould not that DMIPS, means Dhrystone MIPS, so that part should be here, and the disclaimer might as well be.. comp.arch (talk)

Seems like the benchmark has been removed from the table, but the footnote is still there. Should the footnote be removed now?

apple products

@Comp.arch: It seems to me that the little apple cores (Zephyr and Mistral) really should have their own listing on this table. Also, are there cites for the specs of the A11 parts? Dbsseven (talk) 20:16, 18 October 2017 (UTC)

I'm not so sure, either split or not split into separate entries will be misleading. For regular big and LITTLE cores that you can get separate from ARM, you have good info on either. I assume these Apple "LITTLE" cores will also be in-order, but what more is known, pipeline length? But even with all info known, you can't buy them separately, so cache info is always shared, so that's an argument for not splitting info out. comp.arch (talk) 09:18, 19 October 2017 (UTC)

I don't necessarily think it's misleading to include them. They are distinct cores and (I believe) better listed separately, rather than being alluded to in the details of the big cores. (This will also make the big.LITTLE column cleaner for the A10/A11 products.) However, as you point out there will be quite a few of unknowns for Zephyr and Mistral. Dbsseven (talk) 15:20, 19 October 2017 (UTC)

Speculation Abilities and Spectre

It would be interesting and useful to list CPUs speculation abilities (supported or not, max instructions in flight, etc.), and also their vulnerabilities with respect to the Spectre and Meltdown bugs. — Preceding unsigned comment added by 49.255.5.42 (talk) 23:03, 28 February 2018 (UTC)

Add Dhrystone scores

Hi, how would be adding the scores be possible? I benchmarked it on my own iPhone 6S by the way, on iOS 11.1.2, with clang 5.0 (-O3). Athens ms (talk) 17:59, 17 May 2018 (UTC)

If a reliable source cannot be cited then it should not be included. Citing yourself is original research and the previous cite of twitter does not meet the standard of WP:SPS. Dbsseven (talk) 18:14, 17 May 2018 (UTC)

Cortex release dates

I added some release dates for Cortex designs based on the first technical reference manual revision that was not marked confidential. There may be room for disagreement in some cases, but the year should be off by at most one. Vox Sciurorum (talk) 12:08, 23 February 2019 (UTC)

Fujitsu A64FX

I think it would be useful to add it to the list. https://www.fujitsu.com/global/documents/solutions/business-technology/tc/catalog/20180821hotchips30.pdf and https://www.fujitsu.com/global/documents/solutions/business-technology/tc/catalog/20160822hotchips28.pdf for pretty recent information, but there are more materials around the web. This newest I could find is here https://www.hpcuserforum.com/presentations/april2019/Rikenmatsuoka.pdf (and video presentation of it: https://www.youtube.com/watch?v=fU599le3zjc ). The chip is ready and taped out with no bugs and exceeding target performance in 2019Q1, and the full manufacturing of the CPU and the "Post-K" machine pre-production started. The cores, caches, memory systems, are all completely new and not really based on other ARM cores. There is also cross core communication fabric, which connects 48+4 cores, and 4 memory controllers (for 4xHBM2). It looks like a NUMA on a single chip actually, which is quite novel aspect of a design actually. It uses 7nm manufacturing, Armv8.2-A + SVE, with no 32-bit compatibility (only AArch64), 512-bit SIMD width in SVE (which support both wide and narrow floating point types, as well narrow integer packing, some for very high performance calculations and AI/DL), 4x8GiB of HBM2 memory, 256GB/s each, for a total of 1024GB/s peak memory bandwidth, integrated PCIe 3 controller with 16 lanes, and integrated Tofu network logic. Tofu network controllers can inject data directly into specific L2 caches. It has theoretical 2.7TF+ in double precision FP workloads, and achieves 95% of that in some realistic benchmarks. A group of 12 cores, share a common 8MiB L2 cache (16-way associative), that is also connected to NOC fabric. L2 has enough bandwidth to deliver 115GB/s read and 57GB/s write to EACH core. Each core also has own L1 cache. L1D is 64KiB, 4-way, and delivers 230GB/s read, 115GB/s write performance per core. (11.0TB/s total aggregated for entire CPU chip). L1 data cache supports unaligned reads up to 128B/cycle, with no performance degradation. The core itself has 7 stages, and 4-way decode. The decode width can be adjusted dynamically to reduce power consumption, and is done by on-chip power management system. There are 7 main execution units, and 3 register banks for various register types. The claimed power efficiency is >15GF/W. CPU package is 60x60mm. System is compact and water cooled. I couldn't find much more details about microarchitecture, like I$L1, reorder buffer, LDS queue sizes in core and L2 levels, number of physical registers. I am not even sure if the machine is out-of-order or if it has speculative execution. It has a branch prediction tho, and I am sure it is pretty advanced one, possibly using TAGE predictor, or some design borrowed from original ARM core, or SPARC64 VII series. 81.6.34.246 (talk) 06:57, 16 September 2019 (UTC)