Talk:TMS9900

	This article is within the scope of WikiProject Computing, a collaborative effort to improve the coverage of computers, computing, and information technology on Wikipedia. If you would like to participate, please visit the project page, where you can join the discussion and see a list of open tasks.ComputingWikipedia:WikiProject ComputingTemplate:WikiProject ComputingComputing articles
???	This article has not yet received a rating on Wikipedia's content assessment scale.
???	This article has not yet received a rating on the project's importance scale.

Curious about X

The main article says there was a rare and uncommon instruction called "X" - used for executing an instruction that is pointed to, by another register. After the instruction, program flow resumes where the Program Counter used to be.

What is the object code for this instruction?

The main article could be improved by explaining which engineers came up with this instruction. Its probabl use appears to be fairly obvious. It appears to facilitate distributed processing.

Were there any other microprocessors that use this kind of instruction? 216.99.198.99 (talk) 01:34, 21 August 2009 (UTC)[reply]

Execute instructions were well known. The IBM System/360 and DEC PDP-6 and -10 both had them, as did the Varian 620 mini John L (talk) 03:19, 23 August 2009 (UTC)[reply]

Thanks, that is very interesting. 216.99.198.97 (talk) 07:54, 9 September 2009 (UTC)[reply]

RSET instruction

Without having to download and study the TMS9900 instruction set, can anybody brief me on what the RSET instruction did? Was it a software interrupt like the 6502 BRK, but uninterruptible, like an NMI triggered by software?

The main article could be improved by describing the RSET instruction, and noting whether it could bring about a restart, or was it more like a "clear" the bit instruction, similar to RCLR in some microprocessors like the 68000? 216.99.198.28 (talk) 23:12, 6 September 2009 (UTC)[reply]

The book "Fundamentals of TI-99/4A Assembly Language" helps answer this question on page 303. RSET is a control instruction, just like LREX, CKOF, CKON, IDLE, and CRU. The last operation is apparently a hardware operation realized by accessing a particular address in memory without an opcode. That doesn't make sense to me, so maybe someone here at Wiki can explain it, as the only thing that is important is driving the bottom 3 address lines, perhaps by inserting a cartridge that grounds those lines, or raises them up somehow.

If it is helpful, the opcodes are defined in binary as:

RSET ($0360) %0000 0011 0110 0000

IDLE ($0340) %0000 0011 0100 0000

LREX ($03E0) %0000 0011 1110 0000

CKOF ($03C0) %0000 0011 1100 0000

CKON ($03A0) %0000 0011 0110 0000

If the object code looks a little funny to you, or doesn't add up, remember that this is a Big Endian microprocessor. 216.99.198.97 (talk) —Preceding undated comment added 07:22, 9 September 2009 (UTC).[reply]

Whenever a control opcode (listed above) is executed, it apparently affects the bottom3 address lines (bits A0, A1, A2). Since this is a Big Endian microprocessor, am I right in concluding this brings about a massive memory shift? Where the 3 bottom bits are actually the 3 highest bits of addressable memory? Sort of like swapping out entire chunks of addressable memory? 216.99.201.217 (talk) 07:44, 10 September 2009 (UTC)[reply]

It isn't immediately clear to me that the microprocessor is Big Endian. But it is 16 bits wide, so the opcodes are 16 bits wide, that much is clear. But whether the opcode for RSET is stored in memory as $03 followed by $60, or $60 followed by $03, is a question that hasn't been answered so far; depending on the way the question is answered, determines whether the microprocessor is Big Endian or not. —Preceding unsigned comment added by 216.99.201.35 (talk) 03:39, 13 September 2009 (UTC)[reply]

Endianness is one of the most misunderstood things among software developers. The reason is that people get hung up on terminology and lose sight of what is really happening at the hardware level.

First, the TMS9900 is a Big Endian processor. Which bit is called A0 has nothing to do with endianness. There does seem to be some consistency among chip manufacturers regarding this labeling, but that is merely coincidental. For the TMS9900, TI chose A0 to represent the most significant address bit and A14 to be the least significant address bit. They could have labeled them in the reverse order without changing the endianness.

Second, when a RSET instruction executes, the 3 most significant address lines (A0, A1, and A2) are driven Low, High, High, respectively, and the CRUCLK line is pulsed. This combination of signals causes the CRU bus to reset, but does not invoke a memory access. Then the 9900 loads the contents of memory at address 0000 into the Workspace Pointer (WP) register and address 0002 is loaded into the program counter (PC). After this, execution continues at the address loaded into the PC.

If you look at the object code on a Little Endian computer (such as a PC), the RSET instruction may look like 60 03, but on a big endian machine (or with SW that compensates for endianness) you would see 03 60. Because the 9900 is a 16 bit device, the opcode is stored in memory as 0360. Jimwilliams57 (talk) 05:09, 14 September 2009 (UTC)[reply]

You should keep in mind that the so called external instructions, with the mnemonics LREX, RSET, CKON, CKOF and IDLE have their names from their use in the TM 990 mini computers. In addition to their meaning inside the CPU, their full function relies on specific hardware to decode these instructions. What happens when they are executed depends upon that hardware. It is for example possible to include hardware that will decode the RSET instruction to also do a hardware reset of chips in the computer, including the CPU itself. Without such hardware, the only thing that happens is that the CPU disables interrupts, by loading zeroes into ST12-ST15, which is equivalent to executing LIMI 0. The IDLE instruction could turn on an indicator LED, to tell the user the CPU is idle (as was done by the Cortex computer). That computer also took benefit from the CKON and CKOF instructions, but used them to enable and disable a memory mapper circuitry. LREX cause a delayed interrupt after two instructions, by clocking a row of flip-flops with the IAQ signal. By loading proper values into R13-R15, then executing LREX RTWP, the computer would "return" to the desired instruction, execute that one, then come back to a debugger by the interrupt.

But without this external logic, these instructions do nothing, or very little.

Neutrality

There's a neutrality disputed tag on the main page, but no discussion of neutrality in the talk page - what's up? At first reading, the article feels like it's been written by an enthusiast of the chip, but it doesn't seem wildly at variance with NPOV. Rob Burbidge (talk) 12:16, 16 September 2009 (UTC)[reply]