Jump to content

Talk:Physical Address Extension

Page contents not supported in other languages.
From Wikipedia, the free encyclopedia

This is an old revision of this page, as edited by Starvisionstar (talk | contribs) at 11:56, 7 February 2015 (→‎Phrasing in history section re. AMD's changes). The present address (URL) is a permanent link to this revision, which may differ significantly from the current revision.



Archives (Index)

This page is archived by ClueBot III.

Phrasing in history section re. AMD's changes

Seriously, who said "It was extended[when?] by AMD to add a level to the page table hierarchy, to allow it to handle up to 52-bit physical addresses"? Is it said by Jeh? why? Make a further explanation! OK, Jeh, or anyone else, never leave any notes to my own talk page! Janagewen (talk) 02:27, 18 November 2014 (UTC)[reply]

That's a good catch! It isn't true. I don't think I wrote that, but it doesn't matter who wrote it; it's wrong. (Wikipedia wants to focus on fixing things, not on assigning blame.)
The additional level of page table hierarchy is necessary to allow it to handle wider virtual addresses, not physical.
What did happen was that when AMD defined that four-level page table structure for x64, they also spec'd that they were widening the PFN field in the page table, etc., entries... thus allowing more than 36 bits of physical address to come out of the translation. But they didn't make the entries wider. They were already 64 bits wide under 32-bit PAE. The PFN was in bits 12 through 35, bits 36 through 62 were unused. AMD just extended the PFN field to include bits 12 through 51. (Bits 52 through 62 are reserved for the OS, and bit 63 is the NX bit.) This by the way also works on x64 processors when the processor is in 32-bit mode.
Also, NX bit functionality was already there long before AMD started working on x64. So the claim that AMD added NX at this time is wrong too. 32-bit PAE already supported NX.
I can't see why this is related to 64-bit virtual address translation (which is what necessitated the four-level tables) at all.
I don't have time to fix it myself right now, not and have it properly referenced. But I don't have to be the one to fix it.
Aside: You know, a much shorter section head would leave a lot more room for a meaningful edit summary. Jeh (talk) 03:15, 18 November 2014 (UTC)[reply]


Sorry! Janagewen (talk) 03:55, 18 November 2014 (UTC)[reply]
Not a big or even medium deal, just thought I'd mention it. Thank you again for the "catch." Jeh (talk) 04:25, 18 November 2014 (UTC)[reply]
ok, it's fixed. Jeh (talk) 02:46, 30 December 2014 (UTC)[reply]
Aside: The original phrasing was ok, depending on how you interpret the first comma:
"It was extended by AMD to add a level to the page table hierarchy, to allow it to handle up to 52-bit physical addresses, add NX bit functionality, and make it the mandatory memory paging model in long mode."
If you assume that this means that adding a level to the page table hierarchy was done to allow handling of 52-bit PAs, that's incorrect. But if you regard this as describing four independent changes, i.e. "adding a level to the page table hierarchy" and "to allow it to handle up to 52-bit physical addresses" are separate steps with the second not depending on the first, then that correctly describes the changes AMD made. As I noted previously, the additional "level" was added to support wider virtual addresses... but that does not mean that AMD did not also extend the PFN field to support up to 52-bit physical addresses.
Further aside to Janagewen or whatever IP or nick you show up with next: I went through the page history. I did not write the text in question. I'm not going to give a diff to identify who did write it (or when) because, as I said above, what we do here on WP is identify and fix errors, not try to call out those who made them. (But if you really care, you can find it just as I did.) Depending on interpretation this wasn't even an error, just phrasing that could be misinterpreted. Nevertheless, thanks for calling attention to it so that it could be improved. Jeh (talk) 19:19, 30 December 2014 (UTC)[reply]
Es ist schade, a nonsense explanation. Najagewinnen (talk) 00:47, 5 February 2015 (UTC)[reply]
Can you explain exactly how you think it is nonsense? 'cause I'm not seeing it. Perhaps someone else will be able to offer their evaluation of the original text, and/or of my explanation above, and/or of the clarified text in the article (an edit that was made in response to Janagewen's message above).
In any case, the article text was clarified some time ago.
Your removal of the clarified text was unjustified as it a) describes something that did happen in PAE's "History" (the section title) and b) explains what "This" refers to in the sentence that follows, "This version of PAE...". I have therefore restored the sentence. Jeh (talk) 02:42, 5 February 2015 (UTC)[reply]
OK, let me explain it for you. The removal text is nonsense, because PAE is a optional feature for IA-32 architecture, and AMD64 is another architecture, not IA-32, put it as one integrated component rather than a feature. And the references somebody made does really seem nonsense, and tends to mislead. For your response to question of this section, I've seen nothing useful or meaningful at all, and obviously failed to explain it, so I said it non-sense. I am a computer architecture learner getting touch with x86 architecture for more than 12 years. So I am very sorry, your explanation is nonsense. Najagewinnen (talk) 08:29, 5 February 2015 (UTC)[reply]
The AMD64 (or x64, or x86-64, whatever) architecture is not regarded as "another" architecture, independent of and separate from x86. Rather, x64 includes all of x86 as a subset. That's why you can boot a 32-bit x86 OS on an AMD 64-bit processor and run 32-bit apps and device drivers and it all "just works", completely binary compatible.
When AMD defined x64, they included PAE. They started with the x86 version of PAE, and extended it, as is described in the article. Just as they started with everything else that was in x86, and extended it. (More and wider registers, etc.) AMD's documentation for x64 states clearly that these processors boot into 32-bit, x86-compatible mode - called "legacy mode"; that PAE, just as it is defined for 32-bit-only x86 processors, is available in legacy mode; that PAE must be enabled before switching to long mode (64-bit mode), and that PAE must remain enabled while in long mode. So PAE on x64 is not some sort of very different thing, defined independently of x86. It is PAE as it was on x86, but with a fourth level added to the page table hierarchy.
The fact that PAE was a late-added feature to x86, but was defined from the start as being part of x64 (and not optional - you can't turn off the PAE bit while in long mode, or the machine will GPF), is irrelevant.
The reference given (page 120 of the AMD64 Architecture Programmer’s Manual, Volume 2: System Programming) is absolutely clear on this, and not "misleading". Just because you disagree with it doesn't mean it's misleading. Maybe you just don't understand it yet.
Please note also this from page 437, same book: "Long mode requires the use of physical-address extensions (PAE) in order to support physical-address sizes greater than 32 bits." You can't just deny that by claiming "that's nonsense." AMD is using the term "PAE" to include the addressing mode that's used while in long mode, not just the x86 form of PAE. And Wikipedia must follow its sources.
However, you have called my attention to the lede sentence, which I will now fix. Jeh (talk) 10:38, 5 February 2015 (UTC)[reply]
I have to declare that I am not Janagewen, in order not to be reported by Jeh and blocked. But for Jeh's viewpoint above, I should have to say it is not 100 percent correct. Let the people from AMD or Intel further explain this question. Let this discussion stay! Starvisionstar (talk) 05:55, 7 February 2015 (UTC)[reply]
Some a person whose IP from China mainland reported me as sock puppet of Janagewen. But the question to me is that how could he or she prove that he or she is Chinese? The can I call it nationality puppet? OK, that does not matter. The matter is that, PAE is short for Physical Addressing Extension, pay attention to the word Extension! Under AMD64 or x64 architecture, the bit width of linear address is 64-bit (48-bit implemented), so there is no needing to extend physical addressing at all! So talking about PAE for Long mode or IA-32e mode is meaningless and a bit mislead. Frankly and obviously, AMD64 is paging only architecture, so paging is enabled without needing mentioned at all. And Physical Addressing Extension is a processor feature not architecture feature. Who is confused, who is not confused? I just clear this very fact but being attack by so many and many strange people. Do please leave a person a bit drop of respect, ok? At least, I paid 4 years on computer science in college, I tried to dip into the real computers to inspect the actual bit width supported by each kind of physical processors to re-arrange that stupid x86 table. What all I done here is not disruptive edits at all! Starvisionstar (talk) 11:56, 7 February 2015 (UTC)[reply]
Retrieved from "https://en.wikipedia.org/w/index.php?title=Talk:Physical_Address_Extension&oldid=646026280"