Talk:X86-64

Redundant lists of implementations?

X86-64#AMD64 lists AMD's AMD64 processors at the beginning and also in the "Implementations" subsection. The same is true for Intel's Intel64 processors in X86-64#Intel64 and its "Implementations" subsection. Should one of each of those pairs be removed? Guy Harris (talk) 23:07, 14 February 2015 (UTC)

Hello! That's a good point, went ahead and deduplicated the content. Please check it out. — Dsimic (talk | contribs) 23:21, 14 February 2015 (UTC)

Looks good. Jeh (talk) 23:50, 14 February 2015 (UTC)

Would a list like the one that used to be at the beginning of X86-64#Intel64 be better in its "Implementations" subsection? The AMD list just goes by brand names; the Intel list breaks things up by a combination of brand names (Atom) and microarchitecture, but perhaps something such as

Intel's processors implementing the Intel64 architecture include the Pentium 4 F-series/5x1 series, 506, and 516, Celeron D models 3x1, 3x6, 355, 347, 352, 360, and 365 and all later Celerons, all models of Xeon since "Nocona", all models of Pentium Dual-Core processors since "Merom-2M", the Atom 230, 330, D410, D425, D510, D525, N450, N455, N470, N475, N550, N570, N2600 and N2800, and all versions of the Pentium D, Pentium Extreme Edition, Core 2, Core i7, Core i5, and Core i3 processors.

would work? Guy Harris (talk) 01:06, 15 February 2015 (UTC)

Hm, a more detailed breakdown we have in the article might actually be beneficial, but then again, the version you've proposed above reads much better. While thinking a bit more about it, your version would actually be better; for example, we'd also have to mention Xeon CPUs in the last bullet point, and that would be super redundant. So, I'd say you should go ahead and put your version into the article. — Dsimic (talk | contribs) 01:36, 15 February 2015 (UTC)

Done, but there's still redundancy in there; some of the material is historical and perhaps should be moved to the History section. Thanks for all your work on this! Guy Harris (talk) 01:55, 15 February 2015 (UTC)

Ah, I did nothing special, thank you for all your hard work! This edit should take care of separating most of the historical data and actual Intel 64 implementations. — Dsimic (talk | contribs) 02:52, 15 February 2015 (UTC)

Paging and x86-64

This is quite an interesting and important thing which might always confuse beginners trying to get in touch with x86-64 architecture. Some might confuse and mistake x86-64 architecture is an 48-bit architecture, no, that is absolutely wrong. x86-64 is a real 64-bit architecture, 64-bit(48-bit implemented) virtual address and 52-bit(48-bit implemented) physical address for AMD64, 64-bit(48-bit implemented) virtual address and 46-bit(fully implemented for latest Xeon processors) physical address for Intel64. 64-bit virtual/linear address is further paged into four levels, the top level is PML4, Page-map level-4, ranging from 9-bit (48-bit LA) through 25-bit (64-bit LA), leaving other three levels as 9-bit each for walking through a 4-KiB (12-bit) page. So if future x86-64 processors could fully implement 64-bit virtual address, this paging schema would not be changed. For AMD64 processor, under legacy mode, it could address up to 40 or 48-bit physical space when PAE enabled.

Another thing should also be paid attention to, the PAE capability is irrelative with it of IMC, Integrated Memory Controller. The actual maximum memory support is much less than it, but large physical space could enable devices to map their resources into this space, making expanded memory possible too. — Preceding unsigned comment added by 221.9.23.11 (talk) 02:09, 15 February 2015 (UTC)

Hello! Umh, sorry but I'm having slight difficulties understanding what are your actual suggestions on improving the article? Just as a note, talk pages should focus on article improvements; please see WP:NOTFORUM for further information. — Dsimic (talk | contribs) 02:56, 15 February 2015 (UTC)

No, the main article should also talk about something within this section. OK, guys, this is Janagewen! Would you please lock all the IP addresses within my reach. Then I would not be able to visit Wikipedia.org website. If you could help me lock all the IPs, I would say thank you to you guys! 221.9.23.11 (talk) 03:08, 15 February 2015 (UTC)

Nobody is claiming it is a 48-bit processor or that it is not a "real 64-bit architecture". However, translation of more than 48-bit virtual addresses will almost certainly involve a change to the page table structure. I would even suggest that anyone who suggests otherwise does not really understand the ramifications of what they're claiming.

The PML4 at present can only be 512 entries long, as it is indexed by only 9 bits (bits 39 through 47 of the v.a.). Now let's suppose we allow 64 bits of v.a. with no change to the page table hierarchy. Then the index value to the PML4 table would be 25 bits wide (the 9 bits currently implemented, plus 16 more). To allow all possible index values the PML4 table would therefore have to be 2²⁵ or 32x1024² entries long. Since each entry is eight bytes this would occupy 256 MiB. That's 256 MiB of not-pageable, physically contiguous RAM. That seems like rather a large memory requirement, even with modern multi-GiB RAM configurations, especially since all three major OSs that run on x86-64 use a different PML4 table for each process. With just 16 processes you would need 4 GiB of RAM just for the processes' PML4 tables. I don't think that is a viable approach.

No, the most reasonable way to implement more bits of VA would be to add more levels to the page table hierarchy, exactly analagous to how the PML4 table was added to the three-level PAE design. The most obvious design would have a 5th-level table (PML5?) indexed by bits 48 through 56 of the VA, and a 128-entry 6th-level table, with its PA in CR3, indexed by bits 57 through 63. (Maybe when they do that they can get rid of the silly special names for each level in the hierarchy and just call them page tables levels 1 through 6!) Jeh (talk) 10:34, 15 February 2015 (UTC)

No, completely no! There would be no PML5 or PMLn. — Preceding unsigned comment added by 192.154.200.6 (talk) 22:58, 28 September 2015 (UTC)

Why not? It would certainly work. How do you know this with such certainty? Jeh (talk) 05:26, 1 October 2015 (UTC)

... actually it doesn't matter. All of this is speculation. WP doesn't publish editors' speculation. I'll be archiving this section as irrelevant to improving the article. Jeh (talk) 05:26, 1 October 2015 (UTC)

Hello, 192.154.200.6. There is only PML4, and whether there would be PML5, we are not so sure at this moment. Hello, Jeh. We have no ideas whether it would certainly work. Do you have any book or document to prove your words? EhietGeht (talk) 06:15, 1 October 2015 (UTC)

Please. This is a standard technique for implementing sparse arrays, taught in every data structure class, implemented in many many cases. Specifically for address translation, some older processors (like the VAX) use a single level of PT lookup. x86 without PAE uses two levels. x86 PAE uses three levels. x64 long mode, aka IA-32e paging by Intel's naming, uses four levels. There is no reason to think that the technique would magically stop working at level five or six. I'm not claiming it's the best way to implement 16 more bits of virtual address (there might be other methods that would scale better) but yes, it would certainly work. It already does. And it would be a simple set of changes to existing code. Jeh (talk) 05:20, 2 October 2015 (UTC)

Hello, Jeh. We have no information on that right now, and we do not speculate any possibility. EhietGeht (talk) 22:30, 2 October 2015 (UTC)

Beg pardon, but we don't include speculation in articles. This is a talk page. I was responding to a claim by 221.9.23.11 that x64's current address translation scheme could support 64-bit virtual addresses as x64 is currently defined, specifically

"So if future x86-64 processors could fully implement 64-bit virtual address, this paging schema would not be changed. 221.9.23.11 (talk) 02:09, 15 February 2015 (UTC)"

That was, and remains, a false claim. My suggestion that more levels could be added to the PT hierarchy was an example of the sort of thing that would have to be done for x64 to implement 64-bit VAs. Talk pages are for discussing improvements to the article, but that "restriction" is interpreted quite broadly. It does include discussion of why an editor's claim is wrong. It is much better to head off such things before they get into articles. Jeh (talk) 22:49, 2 October 2015 (UTC)

btw, thank you for using regular talk page formatting! That did not go unnoticed. Jeh (talk) 22:49, 2 October 2015 (UTC)

Hello, Jeh. We do not have any idea about that claim, and we do not either speculate its correctness. EhietGeht (talk) 23:03, 2 October 2015 (UTC)

On the contrary, we have a perfectly good "idea" about the claim. The fact that the paging scheme defined for x64 is limited to 48-bit virtual addresses is exactly described in both AMD and Intel's docs (as profusely linked already). The diagrams of address translation in those documents clearly show that bits 48 through 63 of the VA do not participate in address translation in the current scheme. Ergo, to translate even one more bit of VA, let alone 16 more bits, the scheme would have to change. QED.

As for what "we do not" do, you are free to refrain from what you regard as "speculation." For myself, I disagree with that characterization of my responses, nor does "WP does not publish speculation" strictly apply to talk pages. I acknowledge that you have a different opinion. Let's leave it at that, please. Jeh (talk) 23:24, 2 October 2015 (UTC)

Hello, Jeh. I have to make clear that everything you mentioned here or someone else could only be a speculation. Even let me to speculate your mentioned PML5 or PMLn are far more practical than what we expect. At least at this moment, we do not want to waste that huge cost for additional paging level(s). So we do not have any word around that presumption. EhietGeht (talk) 00:27, 3 October 2015 (UTC)

Hello, 221.9.23.11. We have no ideas that if future x86-64 processors could fully implement 64-bit virtual address, this paging schema would not be changed, because there is no documents to prove what you said. But the actual maximum memory support is much less than it is incorrect, the physical memory could be supplemented with a second processor attached on the Hyper Transport Bus, the MPS BIOS would map the physical memory space to these different physical regions. So no matter 40-bit or 48-bit physical address space could possibly be reached without any doubt. EhietGeht (talk) 00:49, 3 October 2015 (UTC)

Shall We Further Extend the Section Intel 64 History?

“ When engineers at Intel started with a “clean sheet of paper” in 1991, it was no surprise that two schools of thought emerged: one to extend CISC IA-32 instructions to support 64-bits, and another to introduce a cleaner RISC style instruction set with the 64-bit support (while maintaining the old instructions for compatibility). While we settled on the RISC approach for a new 64-bit architecture, the attractive idea of extending IA-32 for 64-bit addressing was revisited several times within Intel. It turns out that, for all the marketing charm that a simplistic idea like adding 64-bit addressing to IA-32 holds, in reality that approach would not yield the long-term value we needed. We didn’t figure it out right away, but the RISC approach faced the same reality. ”

The above words are directly referenced from Foreword of Itanium Architecture for Software Developers by Walter Triebel, Intel Press 2000, ISBN: 0970284640. Focusing on the date, 1991, possibly guesses would easily be put to consideration of Intel's own 64-bit version of IA-32 more than a decade before Yamhill rumoured. 175.17.63.223 (talk) 01:52, 15 September 2015 (UTC)

x64

It should be clearly noted that the term "x64" is wrong and only used by two companies. The correct terms used by Intel and AMD are "x86_64" and "amd64". 193.166.70.166 (talk) 12:51, 30 September 2015 (UTC)

Incorrect on several points, I'm afraid, particularly the notion that "x64" is somehow "wrong". It isn't specific to either Intel or AMD but that doesn't make it wrong.

“ x64 is a generic name for the 64-bit extensions to Intel's and AMD's 32-bit x86 instruction set architecture (ISA). AMD introduced the first version of x64, initially called x86-64 and later renamed AMD64. Intel named their implementation IA-32e and then EMT64. ”

That's from Introduction to x64 Assembly, an article at intel.com. Jeh (talk) 13:46, 30 September 2015 (UTC)

Hello, 193.166.70.166, thank you for figuring out x64. But your description is incorrect. Intel uses IA-32e while AMD uses AMD64 in their official documents. So many software have already used x64, x86-64 and x86_64 to refer to this instruction set. As to the main article, because it is written by kids or hobbies rather than professionals or experts on computer science. So we could not have a fair judgement. But you are welcome to help improve it. EhietGeht (talk) 06:09, 01 October 2015 (UTC)

Intel now uses Intel64 as the marketing name, but still uses "IA-32e" internally. See section 4.5 of Intel® 64 and IA-32 Architectures Software Developer’s Manual, where they describe "IA-32e paging", but then look at the title on the cover! Jeh (talk) 04:57, 2 October 2015 (UTC)