Talk:X86-64

Shall We Further Extend the Section Intel 64 History?

“ When engineers at Intel started with a “clean sheet of paper” in 1991, it was no surprise that two schools of thought emerged: one to extend CISC IA-32 instructions to support 64-bits, and another to introduce a cleaner RISC style instruction set with the 64-bit support (while maintaining the old instructions for compatibility). While we settled on the RISC approach for a new 64-bit architecture, the attractive idea of extending IA-32 for 64-bit addressing was revisited several times within Intel. It turns out that, for all the marketing charm that a simplistic idea like adding 64-bit addressing to IA-32 holds, in reality that approach would not yield the long-term value we needed. We didn’t figure it out right away, but the RISC approach faced the same reality. ”

The above words are directly referenced from Foreword of Itanium Architecture for Software Developers by Walter Triebel, Intel Press 2000, ISBN: 0970284640. Focusing on the date, 1991, possibly guesses would easily be put to consideration of Intel's own 64-bit version of IA-32 more than a decade before Yamhill rumoured. 175.17.63.223 (talk) 01:52, 15 September 2015 (UTC)

x64

It should be clearly noted that the term "x64" is wrong and only used by two companies. The correct terms used by Intel and AMD are "x86_64" and "amd64". 193.166.70.166 (talk) 12:51, 30 September 2015 (UTC)

Incorrect on several points, I'm afraid, particularly the notion that "x64" is somehow "wrong". It isn't specific to either Intel or AMD but that doesn't make it wrong.

“ x64 is a generic name for the 64-bit extensions to Intel's and AMD's 32-bit x86 instruction set architecture (ISA). AMD introduced the first version of x64, initially called x86-64 and later renamed AMD64. Intel named their implementation IA-32e and then EMT64. ”

That's from Introduction to x64 Assembly, an article at intel.com. Jeh (talk) 13:46, 30 September 2015 (UTC)

Hello, 193.166.70.166, thank you for figuring out x64. But your description is incorrect. Intel uses IA-32e while AMD uses AMD64 in their official documents. So many software have already used x64, x86-64 and x86_64 to refer to this instruction set. As to the main article, because it is written by kids or hobbies rather than professionals or experts on computer science. So we could not have a fair judgement. But you are welcome to help improve it. EhietGeht (talk) 06:09, 01 October 2015 (UTC)

Intel now uses Intel64 as the marketing name, but still uses "IA-32e" internally. See section 4.5 of Intel® 64 and IA-32 Architectures Software Developer’s Manual, where they describe "IA-32e paging", but then look at the title on the cover! Jeh (talk) 04:57, 2 October 2015 (UTC)

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1. Where does x64 come from?

Windows XP 64-Bit Edition for 64-Bit Extended System was the very first product for AMD64 architecture released in September, 2003, and it was later renamed to Windows XP Professional x64 in late 2004.

Incorrect. What Microsoft shipped in 2003 was Server 2003 for Itanium. x64 versions of Windows XP and Server 2003 didn't RTM until March 2005. I believe the term "x64", as an obvious parallel to "x86", had been used earlier. "x64" is certainly all over a lot of Linux distro file names. Jeh (talk) 22:53, 9 October 2015 (UTC)

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You will not find an "official" date for the "x64" term from Intel or AMD because to neither of them is it an official term. Forums are user-contributed content and are not considered reliable sources on Wikipedia. Re Windows versions, please see Timeline of Microsoft Windows. Jeh (talk) 02:46, 10 October 2015 (UTC)

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I don't have a source for the origin of the term "x64". (Which is why I said "I believe...") Perhaps you could find one. We know that both Solaris and Oracle use the term "officially" but I haven't been able to find a RS for their first use (and Sun/Solaris is now part of Oracle). It is clear the XP and Server 2003 for x64, which RTMd in 2005, were an official use, but my point is simply that the term's first use as part of a Microsoft product name cannot be used as proof that Microsoft invented the term, so we can't make that claim. Jeh (talk) 04:03, 10 October 2015 (UTC)

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Nope. If you'll notice, I voiced an opinion contrary to 193.166.70.166's. But by all means, if you think that, create an WP:SPI. I will be happy to see this speculation about me definitively dismissed. Jeh (talk) 06:07, 10 October 2015 (UTC)

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The wording 64-bit instruction set of x86 processor would be very confusing. To many, if it's an "x86 processor" then it isn't 64-bit. Note for example that 64-bit Windows stores 32-bit executables in \Program files (x86). If one interprets "x86 processor" to mean a 32-bit processor, which is a very common interpretation, then such a processor flatly cannot have a "64-bit instruction set". On the other hand, a 32-bit instruction set can most certainly be changed, enhanced, extended, etc., to include 64-bit support, and that instruction set implemented by a 64-bit processor. Jeh (talk) 22:40, 9 October 2015 (UTC)

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Well, no, they wouldn't have said exactly that... since "x86", being non-manufacturer-specific, is not an AMD official term (nor an Intel official term).

I didn't say "x86 processor" is purely a 32-bit processor. I said it is widely understood to be that.

Previously you noted that in an Intel book you found the text "extend CISC IA-32 instructions to support 64-bits," and now here you are claiming that the result of such an effort should not be called a "version" of the IA-32 (or, generically, x86) instruction set. In fact, these two wordings are perfectly compatible with each other.

The full details are these: An x64 processor in legacy mode (which is how they come up after a reset) supports the 32-bit x86 instruction set, with the added mechanism to switch to long mode. Once in long mode the processor then supports either the Intel64 or AMD64 instruction set depending on manufacturer (these are nearly identical), generically called the "x64" or "x86-64" instruction set. This includes "compatibility mode", a 32-bit mode available "within" long mode, which provides practically the entire 32-bit x86 instruction set to applications.

But that's a really long description, you don't put such in the article lede. For the article lede, "64-bit version of x86 instruction set" is an easy way to introduce the concept and perfectly suitable for the lede; the details are for the article body. Jeh (talk) 03:03, 10 October 2015 (UTC)

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As you said: AMD documents state " "The AMD64 architecture is a simple yet powerful 64-bit, backward-compatible extension of the industry-standard (legacy) x86 architecture." That's a "horse's mouth" source. That and the statement you're arguing against are semantically equivalent; we do not need to find sources for exact phrasing and word choice. If you're quibbling that "version" is something different enough from "extension" to need another source, you are simply wrong; you are arguing over a distinction that does not make a difference. (Most "extensions" can indeed be called "versions", but not every "version" is an "extension.") Jeh (talk) 04:12, 10 October 2015 (UTC)

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The phrase from the AMD doc that you previously quoted is completely sufficient reference. The points you raised such as elimination of segmentation (um, well, but segments are still operational in compatibility mode! They have to be, for 32-bit protected mode code to work right) and additional registers are entirely compatible with the word "version". I think the real problem is that you do not understand the full scope of meanings to which "version" can refer: It can include things added, things left out, existing things changed. If anything we could argue that the AMD doc's use of "extension" is misleading (one of your favorite words) because if we remember that segmentation is not present in long mode, the long mode architecture cannot be said to be a pure "extension", since it left some things out! Bah. There's no problem with the existing text. Jeh (talk) 04:59, 10 October 2015 (UTC)

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Yes, I'm welcome to agree with Jeh 100% and Janagawen 0%. x86 is a family of instruction sets (16-bit x86, 32-bit x86 or IA-32, 64-bit x86 or x86-64), just as MIPS is a family of instruction sets (MIPS I, MIPS II, MIPS III, MIPS IV, etc.) and System/3x0 is a family of instruction sets (32-bit-with-24-bit-addressing System/360, 32-bit-with-24-bit-addressing System/370, 32-bit-with-31-bit-addressing System/370-XA, 64-bit z/Architecture), and so on. Guy Harris (talk) 06:56, 10 October 2015 (UTC)

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There exists a family of instruction set architectures that includes 16-bit x86 (as implemented in the 8086/8088, 80186/80188, and 80286), 32-bit x86 (as implemented in the 80386 and all later 32-bit processors), and 64-bit x86 (as implemented in the Opteron and all later 64-bit processors). 32-bit x86, or IA-32, was a backwards-compatible extension of 16-bit x86, and 64-bit x86, or x86-64, was a backwards-compatible extension of 32-bit x86. That family is what the x86 page covers.

Intel even spoke of "32-Bit Extensions of the Instruction Set" in their "Introduction to the 80386" document, saying

With the 80386, the 86/186/286 instruction set is extended in two orthogonal directions: 32-bit forms of all 16-bit instructions are added to support the 32- bit data types, and 32-bit addressing modes are made available for all instructions referencing memory. This orthogonal instruction set extension is accomplished having a Default (D) bit in the code seg- ment descriptor, and by having 2 prefixes to the instruction set.

so IA-32 was just like x86-64 in that regard, and there's no reason to treat them differently. The only thing that led to "x86" being used when "IA-32" was what was meant was that, when x86-64 arrived, most x86 processors were 32-bit rather than 16-bit.

There needs to be some way to refer to the entire family of instruction sets, starting with the 8086 instruction set and going all the way to the instruction set implemented by Skylake processors. If you have a better suggestion for a single name for that entire family, please suggest it; x86-64 would then be the 64-bit version of that instruction set, or the 32-bit member of that instruction set family, just as IA-32 would be the 32-bit version or member. Guy Harris (talk) 03:41, 11 October 2015 (UTC)

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Do you also suggest that "32-bit instruction set of an x86 processor" is a better description of IA-32 than "32-bit version of the x86 instruction set"? If not, why not? I don't think the fact that "x86-64" begins with "x86" is enough of a reason. Guy Harris (talk) 04:56, 11 October 2015 (UTC)

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No, x86-64 isn't any more special than IA-32. It's distinct from IA-32, but that's because IA-32 is a 32-bit instruction set, and x86-64 is a 64-bit instruction set; both are in the same family as the original 16-bit 8086/8088/80186/80188/80286 instruction set, namely the x86 family. That original instruction set was extended to 32 bits with IA-32 and IA-32 was extended to 64 bits with x86-64.

x86-64 isn't a replacement for Itanium, it's an attempt by AMD to compete with Intel in the 64-bit market. AMD's original press release emphasizes the "you can switch to 64-bit computing as necessary, rather than having to make a big change right now" aspect of x86-64. Intel and HP had tied up IA-64 with patents so that AMD couldn't implement it themselves. As AMD's x86-64 processors implemented x86-64 and IA-32 with the same circuitry (x86-64 being a compatible superset of IA-32), their processors were not only fast 64-bit processors, they were also fast 32-bit processors running IA-32 code - unlike the original IA-64 processors, whose IA-32 implementations were slow. So x86-64 processors could be put into ordinary PCs running 32-bit code, especially starting with the 64-bit Athlons, whereas IA-64 processors couldn't. It was intended from the beginning to be an extension of IA-32, so that x86-64 processors could be used instead of IA-32 processors, even running 32-bit-only code, just as IA-32 was intended from the beginning to be an extension of 16-bit x86, so that IA-32 processors could be used instead of 16-bit x86 processors, even running 16-bit-only code. So it's just like IA-32 in that way, and it's valid to refer to it as the 64-bit version of the underlying instruction set, just as IA-32 is the 32-bit version.

x86-64 never was "completely new" in the way that IA-64 was; it was a compatible extension, rather than an incompatible new instruction set like IA-64. The AMD press release says "AMD plans to extend the x86 instruction set to include a 64-bit mode", just as Intel said that "With the 80386, the 86/186/286 instruction set is extended in two orthogonal directions".

Intel don't call Intel 64 "a 64-bit version of IA-32", because it's a 64-bit member of the x86 family of instruction sets; it's not a 64-bit version of IA-32, because IA-32 is the 32-bit member of that family. It's a 64-bit version of x86, just as IA-32 is a 32-bit version of x86. AMD speak of it as an extension to x86, similar to the extension to 32 bits (and to an extension from 8 bits to 16 bits, but it's not clear what they're talking about there - the 8086 and 8088 were 16-bit processors, although the 8088 had an 8-bit external bus) in another press release.

So x86-64 is an extension of the x86 architecture to support 64-bit computing, just as IA-32 was an extension to support 32-bit computing.

And as for "alternative choices", there were no alternative compatible choices to x86-64, either, and if you consider incompatible choices, there were alternative choices to IA-32, such as 68k. Yes, IA-64 processors could run IA-32 applications, but not very well.

As for "the 16-bit architecture evolves into this IA-32 architecture", IA-32 evolved into x86-64, just as 16-bit x86 evolved into IA-32.Guy Harris (talk) 09:51, 11 October 2015 (UTC)

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"I mean the successors of the IA-32 architecture, Itanium and AMD64". Itanium wasn't a successor in any technical sense; the two instruction sets are radically different. Intel intended that it replace IA-32 from a marketing point of view, but assembler programmers and compiler writers will be able to use next to nothing of their understanding of IA-32 when writing software for IA-64. AMD64, however, was a backwards-compatible extension of IA-32, adding the REX prefix to allow access to additional GPRs, IP-relative addressing modes, and 64-bit operands, and another operand-width bit in segment descriptors; in legacy mode, the values used by REX prefixes are interpreted as single-byte increment-register and decrement-register instructions, but, in long mode, they're interpreted as REX prefixes. That means you have to use multi-byte versions of register increment and decrement instructions in long mode, but that's the only incompatibility between IA-32 and x86-64 in long mode.

So x86-64 looks, with the exception of the single-byte increment-register and decrement-register instructions, like "IA-32 with more stuff added on"; that's more like "English in 1988", which lacked such important features as the noun "selfie" and the verb "google", vs. "English in 2015", with those additions, than like Spanish and Latin. No radical change there, just change like the 16-bit x86 instruction set to IA-32, with the addition of additional addressing modes, an operand-width bit in segment descriptors, etc..

"Spanish and Italian languages are evolved from Latin language" Without "backwards compatibility" - for example, both Spanish and Italian have significantly simpler grammars than Latin. x86-64 is backwards-compatible with IA-32, so that's not a good example - it's more like the difference between ARM A32 and A64, where the instructions changed in an incompatible fashion (for example, most of the conditional execution capabilities were removed in A64). IA-32 to x86-64 is more like the evolution from SPARC v8 to SPARC v9, or from System/390 to z/Architecture, or from PA-RISC 1.1 to PA-RISC 2.0, or from MIPS II to MIPS III, or from 32-bit PowerPC to 64-bit PowerPC.

And calling x86-64 the 64-bit version of x86 doesn't do anything to make people think it's another architecture from x86 - in fact, it more strongly emphasizes that it's a version of x86. Not all x86 processors support x86-64, so it's not the "64-bit instruction set of an x86 processor"; only 64-bit x86 processors support it, just as only 32-bit and 64-bit x86 processors support IA-32. x86-64 is a superset of IA-32, just as IA-32 is a superset of 16-bit x86; an x86 processor could:

• support 16-bit x86 without virtual memory (8086/8088, 80186/80188);

• support 16-bit x86 with segmented virtual memory (80286);

• support 16-bit x86 and 32-bit x86 with segmented and paged virtual memory (80386 and later IA-32-only processors);

• support 16-bit x86 and 32-bit x86 with segmented and paged virtual memory and 64-bit x86 with paged virtual memory (x86-64 processors). Guy Harris (talk) 18:24, 11 October 2015 (UTC)

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And IA-32 is different from 16-bit x86. Speaking of x86 as a "consistent architecture" is a bit bogus, given that it's an architecture with stuff added through a variety of hacks. I don't consider the lack of segmentation in x86-64 to render it somehow not "the 64-bit version of x86" - the 16-bit version has segmentation (which was used significantly), the 32-bit version has segmentation (which was used a lot less), and the 64-bit version doesn't have it in long mode, but still has it in legacy mode. I also don't consider the inability to access the upper 32 bits of the first 8 64-bit GPRs in 32-bit mode to render it not "the 64-bit version of x86". Most of the RISC instructions sets that were extended from 32 bits to 64 bits did so without a mode bit, so there's no notion of "long mode" vs. "legacy mode", and any code can get at all 64 bits of the GPRs on a 64-bit processor. What's different about x86 is that, in real mode, there's no segmentation, so there's no segment descriptor to have a default operand size, and real mode has to be compatible with real mode on 16-bit x86 processors, so the REX prefixes can't be used (they're interpreted as single-byte increment/decrement register instructions), so you can't have 64-bit operands in real mode. So x86-64 isn't as clean an extension of 32-bit x86 to 64 bits as the 64-bit versions of RISC architectures are extensions of the 32-bit versions of those architectures to 64 bits, but it's still an extension of that sort. Guy Harris (talk) 00:20, 12 October 2015 (UTC)

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A nitpick: Segmentation isn't completely absent in long mode. In compatibility mode, which is how 32-bit code runs under a long mode OS, segmented addressing is still there in all its former glory and detail. It rather has to be, or else a great deal of existing 32-bit code (any instruction that uses an explicit segment reference, any code that accesses segment descriptors, any code that writes and reads the segment registers and expects them to function) wouldn't work. So you can't say that segmentation is missing from long mode. Compatibility mode is part of long mode, after all.

Even in 64-bit mode (the other part of long mode), the FS and GS registers still exist and do support non-zero base addresses. (And of course if we're being really thorough we have to mention the four remaining bits of the CS register!) Granted this is nothing like a full implementation of segmentation, but it does mean that you can't say that segmentation is gone completely even from 64-bit mode. Jeh (talk) 06:34, 12 October 2015 (UTC)

As far as I'm concerned, "x86" is the family of instruction sets that includes the 16-bit version without an MMU, the 16-bit version with an MMU, the 32-bit version, and the 64-bit version, so the "difference between x86-64 and x86" is that x86 is the family and x86-64 is the 64-bit member of the family.

x86 has several modes:

• real mode, which is implemented by all four members of the family - including the 64-bit version, where it's a submode of legacy mode;

• 16-bit protected mode, which is implemented by the 16-bit version with an MMU, the 32-bit version, and the 64-bit version as a submode of legacy mode;

• 32-bit protected mode, which is implemented by the 32-bit version and the 64-bit version as a submode of legacy mode;

• virtual 8086 mode, which is implemented by the 32-bit version and the 64-bit version as a submode of legacy mode;

• long mode, which is implemented by the 64-bit version, with 64-bit and compatibility submodes.

Not all of the features of a version of the architecture are accessible from all modes supported by that version of the architecture. You can't do virtual-memory segmentation, or paging, in real mode. You can't do paging in 16-bit protected mode in the 16-bit version with an MMU, although you can run 16-bit protected-mode code in 32-bit protected mode, with or without paging. You can't support linear addresses larger than 32 bits in the 32-bit version. None of this makes x86-64 anything other than the 64-bit version of x86, as far as I'm concerned, and I don't see "64-bit instruction set of x86 processor" as being an improvement over "64-bit version of the x86 instruction set". For one thing, not all x86 processors support a 64-bit instruction set, only the ones that support the 64-bit version do. An "x86 processor" is just a processor that supports some version of the x86 instruction set, just as a MIPS processor is a processor that supports some version of the MIPS instruction set (32-bit or 64-bit), and a SPARC processor is a processor that supports some version of the SPARC instruction set (32-bit or 64-bit), and a PowerPC/Power ISA processor is a processor that supports some version of the PowerPC/Power ISA instruction set (32-bit or 64-bit), and a "System/3x0", or whatever it should be called, is a processor that supports some version of the System/3x0 instruction set (which includes System/360, System/370, System/370-XA, System/370-ESA, System/390, and z/Architecture, so it includes 32-bit with 24-bit physical addresses, 32-bit with 24-bit virtual addresses, 32-bit with 31-bit virtual addresses, 32-bit with multiple address spaces each with 31-bit virtual addresses, and 64-bit with multiple address spaces each with 64-bit virtual addresses; that family of instruction sets also has multiple modes, and not all of the features of a version of the architecture are accessible from all modes, and the behavior of instructions is mode-dependent, e.g. the uppermost 8 bits of addresses are ignored in the 24-bit address modes and the uppermost bit of addresses is ignored in the 31-bit address modes). Guy Harris (talk) 06:47, 12 October 2015 (UTC)

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Discuss all you want, but I can't agree with you, and, unless there's a consensus for "64-bit instruction set of x86 processor", whatever that might mean, I'll revert changes that use it in the main article. Guy Harris (talk) 07:20, 12 October 2015 (UTC)

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I haven't archived anything on this page. Miszabot does not implement an "archive now" command. But I see no reason in keeping stale discussions around for one or two years. Perhaps the section could be hatted to reduce the clutter on the page, and denoted "closed, please do not edit" to avoid escaping archiving. Miszabot is currently set for 30 days; perhaps that is too short. Jeh (talk) 07:43, 12 October 2015 (UTC)

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You haven't changed any essentials from what you've said before; you have merely heaped on more layers of confusing, self-contradictory verbiage. The wording in the article is still fine. "64-bit instruction set of x86 processor" is still potentially confusing to those who do not know the correct meaning of x86. Jeh (talk) 01:21, 11 October 2015 (UTC)

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And if pigs didn't have wings, they couldn't fly. See, they can't! QED. Jeh (talk) 03:34, 11 October 2015 (UTC)

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But x86-64, unlike ARM, is backwards-compatible with IA-32, just as IA-32 was backwards-compatible with 16-bit x86 or, as Intel called 16-bit x86 in the 80386 document I cited, " the 86/186/286 instruction set". So a processor that supported IA-32 and A64 would be different from a processor that supports IA-32 and x86-64 - in fact, a processor that supports x86-64 would, by definition, support IA-32, as x86-64 is a superset of IA-32 (just as a processor that supports IA-32 would, by definition, support 16-bit x86). (In fact, a processor that supported IA-32 and A64 would be somewhat like an ARMv8-A processor, given how different A32/T32 and A64 are. :-))

So there's a very important difference here between, for example, x86-64 and A64, and it's a difference that people reading about x86 and x86-64 need to understand. Guy Harris (talk) 03:48, 11 October 2015 (UTC)

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"52-bit limitation is the architectural limitation for IA-32 architecture processor" There's nothing about 52-bit physical addressing in Volume 3 of the Pentium Pro documentation, the Pentium Pro being the first IA-32 processor with PAE. It's x86-64 that allows 52-bit physical addresses in long and legacy modes; I won't believe that any IA-32 processor could handle 52-bit physical addressing unless I see a see a manual for such a processor ("such a processor" must not support x86-64 - if it supports x86-64, it's an x86-64 processor, not an IA-32 processor). Guy Harris (talk) 10:12, 11 October 2015 (UTC)

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"OK, 52-bit physical address is the limitation of what architecture?"

For Intel, a 64-bit PTE "with IA-32e paging", according to figure 4-11 "Formats of CR3 and Paging-Structure Entries with IA-32e Paging" in Volume 3 of the Intel 64 and IA-32 manual has room for up to 40 bits of "address of 4KB page frame", 30 bits of "address of 2MB page frame", and 22 bits of "address of 1GB page frame". Add to those the number of bits necessary for a byte offset within the page frame, i.e. 12 bits for 4KB, 22 bits for 2MB, and 30 bits for 1GB, and you get 52 bits in all three cases, so, for Intel 64, the architectural physical address limit is 52 bits, unless they really meant to say "reserved" rather than "ignored" for the higher bits. For what it's worth, those bits are all marked as "reserved" in figure 4-7 "Formats of CR3 and Paging-Structure Entries with PAE Paging", so that could be read as implying a larger maximum physical address in legacy mode than in long mode, but I really doubt that's what they had in mind. Perhaps "ignored" means "free for software to use, as the hardware will never ever look at them", which would mean that Intel 64 imposes a hard 52-bit limit that could only be lifted by a new mode, so as not to break operating systems that stuff additional information into those bits.

For AMD, a 64-bit PTE in "long mode", according to figures 5-21 "4-Kbyte PTE—Long Mode", 5-25 "2-Mbyte PDE—Long Mode", and 5-28 "1-Gbyte PDPE—Long Mode" of Volume 2 of the AMD64 documentation, the physical page base address has the same size as it does in the Intel 64 documentation, although the bits above the physical address are marked as "available" rather than "ignored" - I don't know whether that means that they are architecturally available for use by software, which would mean that AMD64 imposes a hard 52-bit limit that could only be lifted by a new mode, so as not to break operating systems that stuff additional information into those bits.

So it appears that the 52-bit physical address is a limitation of x86-64, in both its Intel 64 and AMD64 flavors, and that AMD64 does not change that.

Unfortunately, I can't find any copies of "IA-32 Intel Architecture Software Developer's Manual Volume 3: System Programming Guide" to see whether the 36-bit limitation of Pentium Pro continued all the way with IA-32 until Intel went with x86-64, so there might have been an increase in the maximum physical address size in IA-32 beyond 2³⁶ bytes prior to the introduction of x86-64. Guy Harris (talk) 17:44, 11 October 2015 (UTC)

FYI, Windows regards bits 52 through 62 of the PTE as available for use by the OS, and uses them as a "working set list index" - a way to quickly find, in the WSL, the entry that corresponds to the physical page whose PFN is in the PTE. And of course it treats Intel64 and AMD64 the same in this regard.

In the AMD doc, page 140: "Available to Software (AVL) Bit. These bits are not interpreted by the processor and are available for use by system software." Jeh (talk) 18:23, 11 October 2015 (UTC)

(Comment by block-evading sockpuppet removed per WP:DENY. See Wikipedia:Sockpuppet investigations/Janagewen.)

"The physical address in this paging schema has been expanded from 32-bit to 64-bit" No. The page table entries and page descriptor entries were expanded from 32 bits to 64 bits in PAE. In the 64-bit page table entry for 4K byte pages, bits 0 through 8 are used as flags, bits 9 through 11 are marked as "Avail.", which I'm guessing means "reserved for software, the hardware will never use these", bits 12 through 35 are the physical address, and bits 36 through 63 are reserved (and should be set to 0). That gives 24 bits of physical address, which, combined with 12 bits of byte offset within the page, gives 36 bits of physical address.

"This architecture in architectural-limit might possible point to this PAE paging schema, rather than instruction set architecture." The term "instruction set architecture" is used both to refer just to instruction sets (that's how ARM uses it; A32, T32, and A64 are instruction sets, and various versions of the "ARM architecture" support one or more of those instruction sets, as well as other features such as a memory management unit in some versions) and to refer to other features of the architecture as well, such as the memory management unit. In the case of x86, the "instruction set architecture" also includes the MMU.

I don't have a copy of the last IA-32-only version of Intel's documentation, so I don't know whether it also had a 36-bit limit on physical addresses, i.e. whether it required that bits 36 through 62 must be zero, and bit 63 might be required to be zero or might be the "no execute"/"execute disable" bit.

As for AMD64 and Intel 64, AMD says in Volume 2 of the AMD64 manual that, in a 64-bit PTE, bits 52 through 62 of the PTE are "reserved, MBZ" (Must Be Zero) and that, for the Physical-Page Base Address, "This is an architectural limit. A given implementation may support fewer bits.", so they appear to be saying that 52 bits of physical address is an architectural limit, although, by marking the upper bits as "reserved, MBZ" rather than "available", they might leave open the possibility of going beyond 52 bits without requiring a mode bit - I read "reserved, MBZ" as meaning that an operating system should NOT put its own data into those bits, it should set them to zero, and, in the future, on a system with more than 4 PB of main memory, with a processor doesn't ignore those bits, it could set them to non-zero values to refer to the memory beyond 4 PB. In Volume 3 of the Intel 64/IA-32 manual, however, bits 52 through 58 of the PTE are "ignored" (not "reserved, MBZ"), and bits 59 through 62 are interpreted as "the protection key of the page" if CR4.PKE is 1 and are ignored otherwise. This indicates that it'd be harder for Intel 64 to go above 4 PB of main memory, as its spec appears to promise that some of those bits are "ignored" (so that an operating system could put its own data there, and not fail if those bits are used for the page physical address in the future) and that some of them can be interpreted as the protection key of the page.

"But AMD64 does not extend that architecture for physical addressing in legacy mode." Wrong. Figure 5-12, "PAE Paging Legacy-Mode" of Volume 2 of the AMD64 manual shows bits 12 through 52 - not bits 12 through 35 - being used for the "Physical-Page Base Address".

"Paging, PAE paging are both the processor-side features, they are like some an additional unit attached between processor and system memory" But that's not what it is - x86 processors, starting with the 286, have had the MMU on the CPU chip, unlike, for example, the 68k family, where the MMU wasn't on the CPU chip until the 68030. And both Intel and AMD document the operation of the MMU in the manual for the architecture, so it's not something separate for the architecture.

"You can also compare it with yesterday FPU located aside CPU processor, even though all of them were discussed in most instruction set architecture documents." Yes, and floating point is part of the instruction set architecture as well. Guy Harris (talk) 05:34, 12 October 2015 (UTC)

(Comment by block-evading sockpuppet removed per WP:DENY. See Wikipedia:Sockpuppet investigations/Janagewen.)

The "reserved, MBZ" indication from the AMD doc is all in the "legacy mode" section 5.2. This is what would be used under a 32-bit OS. For a 64-bit OS we want section 5.3, "Long-Mode Page Translation". The PTE, etc., formats shown on page 133, 135, and 137 describe bits 52 through 62 as "available". The description of fields in section 5.4 says that that means "available to software". So, a 64-bit operating system can put its own data into those bits, just as is allowed for bits 9, 10, and 11. (I'm not disputing that writing nonzeroes to bits 52-62 would be disallowed in legacy mode. But that is irrelevant to a 64-bit OS.) As I mentioned previously, x64 Windows most definitely uses them (for a "working set list index" value). (See Windows Internals, Sixth Edition, part 2, page 266.)

So, yes, there is room to think that the architectural limit of 4 PB of RAM could be easily raised, without breaking existing OS code... but only for a legacy mode (32-bit) OS! For a long mode OS we are just going to be "stuck" at 4 PB without requiring OS changes. We will just all have to find ways to cope with this crippling restriction. (*grin*)

As for the "software protection key" feature described for Intel64, that appears to be quite new! It isn't in the September 2014 book, but is in the June 2015. Jeh (talk) 06:12, 12 October 2015 (UTC)

Processors are implementations of an architecture, so a "processor feature" may be specified by the architecture. Paging, as well as segmentation, are described in Volume 2 of the "AMD64 Architecture Programmer’s Manual and volume 3 of the Intel 64 and IA-32 Architectures Software Developer’s Manual. Those documents guarantee that all AMD64 processors will do paging in the fashion described in the first of those manuals and all Intel 64 and IA-32 processors will do paging in the fashion described in the second of those manuals; it's not as if each AMD64 processor or each Intel 64 or IA-32 processor gets to implement its own unique form of paging. The whole point of an architecture manual is to eliminate or, at least, minimize the amount of code that has to be changed or written new for a new processor; this includes not only user-mode code but operating system kernel code - the part of the virtual memory code that handles page tables doesn't have to be completely rewritten for each new x86 processor or System/3x0-or-z/Architecture processor, although it might need to change for new versions of some RISC processors where they chose not to put the MMU into the architecture (or even some older CISC processors like that, such as the earlier Motorola 68k processors). So, no, I don't accept any purported explanation of paging being a "processor feature" not connected with the architecture. Paging might not be visible from userland code, and even some kernel code, but there's code that has to manipulate the page tables, and either that code can be the same for all processors, if it's specified as part of the architecture as is the case in x86, or it might have to be different for different processors, if it's not specified.

And Jeh noticed that the description of the PTEs in long mode explicitly says that the bits between the NX bit and the page physical address are "available" for software use, so both AMD64 and Intel 64 will need a mode bit in order to access more than 4 PB of main memory; that limit is specified in architecture manuals, so it's part of the architecture. Guy Harris (talk) 07:04, 12 October 2015 (UTC)