Clock recovery

Some digital data streams, especially high-speed serial data streams (such as the raw stream of data from the magnetic head of a disk drive and serial communication networks such as Ethernet) are sent without an accompanying clock signal. The receiver generates a clock from an approximate frequency reference, and then phase-aligns the clock to the transitions in the data stream with a phase-locked loop (PLL). This is one method of performing a process commonly known as clock and data recovery (CDR). Other methods include the use of a delay-locked loop and oversampling of the data stream. Quality metrics for recovered clock and associated recovered data include jitter and bit error ratio.

Clock recovery is very closely related to the problem of carrier recovery, which is the process of re-creating a phase-locked version of the carrier when a suppressed carrier modulation scheme is used. These problems were first addressed in a 1956 paper, which introduced a clock recovery method now known as the Costas loop. Since then many additional methods have been developed.

In order for this scheme to work, a data stream must transition frequently enough to correct for any drift in the PLL's oscillator. The limit for how long a clock recovery unit can operate without a transition is known as its maximum consecutive identical digits (CID) specification. To ensure frequent transitions, some sort of self-clocking signal is used, often a run length limited encoding; 8b/10b encoding is very common, while Manchester encoding serves the same purpose in old revisions of 802.3 local area networks.

See also

• Phase-locked loop
• 8B/10B encoding
• Eight-to-Fourteen Modulation
• Manchester code
• 64B/66B encoding
• B8ZS encoding
• HDB3 encoding
• Burst mode clock and data recovery
• Jitter