Talk:VHDL

New examples

I have added some new examples (templates) to the VHDL page which i feel are important to understanding VHDL. However, the code is untested (full of syntax errors, i fear) and I am not a native English speaker so the new text might need some cleaning... I was also thinking about adding the RTL representation (i.e. an image) to each template. Would that be of any good? I could also add more examples, but the page is getting messy, so maybe we should start a new page for VHDL examples/templates? Furthermore, i have added a section called "getting started with VHDL" which i feel is important too, given the questions i see on the comp.lang.vhdl and comp.arch.fgpa newsgroups everyday. -- 83.249.212.91 17:11, 16 October 2006 (UTC) VHDL developer

I think it should be reverted because WP is not supposed to be a howto guide. And even more so if your examples haven't even been syntax checked. — RevRagnarok ^{Talk Contrib} 18:26, 14 October 2006 (UTC)

It is not a howto guide. It explains the templates, which is the difference between HDL and programming languages. I think they are very important for understanding the contecp. If you check the Verilog and System Verilog pages, you will notice pretty much the same examples there too. I agree that it is a little messy, but i would rather see it cleaned up than removed. Anyway, I have created images for the example code (yes, they compile just fine) and maybe adding the RTL view for each snippted would make it more understandable. I am still learnng WP and trying to figure out how to uploaded pictures to the page.... -- 83.249.212.91 17:11, 16 October 2006 (UTC)

Misleading statement about VHDL

In the Discussion section the sentence `However, it is easy for the unwary and inexperienced to produce code that simulates successfully [...]' follows immediately the sentence `In this regard, it is considered by some to be superior to Verilog'. This could mislead the reader to think that the second sentence applies specifically to VHDL. In reality it applies to Verilog as well.

I fixed this error. I assume that the flip-flop/latch pitfall doesn't apply to Verilog, but someone please tell me if I'm wrong. -- Heron 19:20, 14 Jul 2004 (UTC)

Actually, the flip-flop/latch pitfall applies to Verilog as well.

I an new to Wikipedia, and I didn't see the discussion page before I edited the statement inder the VHDL discussion. The line I saw today seemed to imply that VHDL could do testbench work, and that verilog was less capable in this regard. In fact, both are very successful at these tasks, so I changed the sentence to reflect this. Gordwait

Hello World

I appreciate that the "Hello World" program is a tradition for languages but I don't really think it helps or adds anything to the article. I personally think that it just confuses matters as it doesn't really bear any relation to the way VHDL is used 99% of the time. Wouldn't it be better to replace it with an example of a simple testbench, or even something simple like a latch?

I agree with the statement to remove the Hello World example. It doesn't even run on the VHDL simulator that comes with my college textbook. Since this isn't really a computer language, but a design language, Hello World doesn't really fit. Bob/Paul

Another Example

 library IEEE;
 use IEEE.std_logic_1164.all;
 entity Shifter is
    port (
       CLK : in STD_LOGIC;
         D : in STD_LOGIC;
         Q : out STD_LOGIC
    );
 end Shifter;
 
 architecture behaviour of Shifter is
 signal rShift : STD_LOGIC_VECTOR(3 downto 0);
 begin
     process(CLK)
     begin
        if CLK'event and CLK='1' then
            rShift(3)<=D;
            rShift(2 downto 0)<=rShift(3 downto 1);
        end if;
     end process;
     Q <= rShift(0);
 end behaviour;

Anyway: It is definitely possible to write "standard" programs in VHDL (for example a sorting algorithm). What I don't know if tshifting thehis "program"-orientated features of the language are actually used often. Where I work we don't use VHDL much for verification, but mostly for synthesis. Can anyone give a comment how widespread and how extensive VHDL is used for verfication ?

I think this example is far more appropriate than the "hello world" example. - James Foster 11:31, 14 Jun 2005 (UTC)

I completely agree with all of the above. I changed the Hello World example to a latch. The above example is good, but it seems more like a queue than a shifter. Maybe if rShift were an output. But then why would you need Q as an output? I don't think the fibonacci example is the best example for this page either. Perhaps we could replace it with the above example? Or maybe a link to VHDL examples. Or a new Wikipedia article dedicated to VHDL code examples. Epachamo 20:52, 20 February 2006 (UTC)

I agree with that - the code above would basically act as a queue, from the looks of it. If you could write and read rShift you could use Q as 'carry out', if you were constructing a rotate-right function for a microprocessor... Mike1024 (t/c) 11:20, 31 March 2006 (UTC)

Actually I think I put this example there. I am not sure what you mean by "queue" (queue sounds to me like you mean a FIFO). This example simply takes the input D, and delays it by 4 clock cycles. This kind of construct is often called Shift_register (In this case serial in, serial out) ? This kind of construction is often used, if you want to "delay" a value by some clock cycles in a pipelined calculation. 84.154.43.11 19:04, 27 December 2006 (UTC)

What's the thought for examples on this section? Do you all only want 1 or 2 or would a few more make sense? Perhaps a counter example, or a small state machine? Or do you prefer to let the external links to VHDL docs provide the greater detail? Also, there is very little said about testbenches. Would it be a benefit to expand on that? (presumably testbench examples would be too long to include) jwilkinson 16:07, 20 April 2006 (UTC)

ASCII is seven bits, not eight bits

And by saying it is eight bits, it leads to confusion. Quoting the article:

"The second issue of IEEE 1076, in 1993, made the syntax more consistent, allowed more flexibility in naming, extended the character type to match the full 8-bit ASCII definition, added the xnor operator, etc."

The ASCII article itself points out that ASCII is seven bits, and while there have been many 8-bit extensions over the decades (from myriad terminal makers and early microcomputers such as the Apple ][), and while the IBM PC's 8-bit character set became a de facto standard, there's no REAL standard for "8-bit ASCII." I read the IEEE 1076 article and saw no mention of ASCII, so I can only wonder if the author of the quoted sentence meant VHDL was extended to use the IBM PC or other 8-bit character set, or if it previously used only a part of the true 7-bit ASCII set and was extended to use all of it, or what.

Comment from Wesley J. Landaker: What VHDL '93 supports is ISO-8859-1; only printable characters are allowed to be used in the actual source (e.g. literal strings, identifiers); the character type itself can hold any value from 0x00-0xff, but they are always interpreted as ISO-8859-1 characters. There are efforts to make VHDL support something better, e.g. UTF-8, but nothing standardized.

Syntax in Fibonacci example

What is up with the end statements in the second example? "end entity Fibonacci;" should be just "end Fibonacci;" as in the first example. Likewise "end architecture Rcingham;" should just be "end Rcingham;", as a synthesis of the code will demonstrate. I'll change it now. ralian 02:29, 22 March 2006 (UTC)

Response to Ralian's note: Newer versions of the standard support full symmetry in keywords bounding longer blocks of VHDL code: 'entity' ends with 'end entity', 'architecture' with 'end architecture', etc. (It definitely makes analysis of longer files easier.) For compatibility with older versions of the standard, omission of 'entity', etc. at the end is allowed. Please do not use synthesis tools as argument for language discussions - they are (by definition) operating on small subset of the language. Jerry_K 20:22, 25 August 2006 (UTC)

Proposal to move VHSIC Hardware Description Language to VHDL

I propose moving this page (VHSIC Hardware Description Language) to VHDL and making the former a redirect to the latter. My rationale is twofold: first, the language is almost universally referred to and known by its abbreviation VHDL rather than the long name for which it stands, and second, for the same rationale that the Wikipedia article on NASA is titled NASA rather than National Aeronautics and Space Administration (which is a redirect to NASA)—NASA is simply the more widely known and used name. Any objections?

—Muhandis 19:15, 24 September 2006 (UTC)

No objections from me, I agree with the move. Vadmium 01:15, 25 September 2006 (UTC)

Works for me. Seems it was moved back in April of this year too. — RevRagnarok ^{Talk Contrib} 11:16, 25 September 2006 (UTC)

• Rename, the problem with the current title is that VHSIC is still an acronym, and one no one ever sees or has heard of. 70.51.11.116 03:22, 26 September 2006 (UTC)

• Support I don't think anyone remembers what the V in VHDL stands for. 132.205.44.134 00:51, 29 September 2006 (UTC)

• Move completed, per above discussion. -GTBacchus^(talk) 18:55, 30 September 2006 (UTC)

History

Is it possible to insert some dates in the History chapter? I think it would be interesting to see how old the language is and that is still used today. Theups 19:41, 30 November 2006 (UTC)

Examples and "end" statements

I just tweaked the examples because there were a few edits previously. I verified every one just now with ModelSim PE 6.2a with my usual command line of vcom -2002 -explicit -lint -source. I know the architecture / entity at the end is optional, but cleaner and easier to debug. Additionally, since this is looking like a small primer, I think it is better to be as verbose as possible in the intro, if somebody becomes more experienced on their own, they learn things like "only an idiot would actually synthesize the AND gate component shown here" or "any engineer who does port mapping by position buys lunch." — RevRagnarok ^{Talk Contrib} 14:48, 4 December 2006 (UTC)

Is it wise, though, for this article to be written as a primer? Compared to C++, which seems to me to be a well-written language article, this one is light on information about the language and heavy on how-tos. For one, the "Getting started with VHDL" section needs to be re-written or deleted, I think. There probably shouldn't be much sample code, either. A few very short examples in context, maybe, but not a series of stand-alone tutorials. I understand the desire to teach the language, but I don't think it's encyclopedic.

Changes I believe should be made:

• Expansion of the Verilog comparison
• Clarification of the difference between VHDL and a software programming language
• Expansion/clarification of the difference between synthesizable code and simulation-only code
• Clearer, more specific differences between '87, '93, etc.
• Revision/deletion of "Getting started" section (a short list of leading tools is one thing, but this appears to be a "recommended tool flow", which may vary greatly from company to company)
• Revision/reorganization/trimming of "Code examples" section (see above)

Comments? -- Fru1tbat 15:49, 4 December 2006 (UTC)

I agree on all points. Back in October (above) I said there was too much howto. However, if it's gonna be there, I'd like it to be correct. I'd recommend you move your list into a {{todo}} — RevRagnarok ^{Talk Contrib} 18:17, 4 December 2006 (UTC)

I agree (but see also my post below). But note that the "getting started" section isnt really about tools, companies or "flows". its about how to get started without paying $$$. For example, if GHDL was more stable, I would have included that too. 83.254.148.19 22:38, 13 December 2006 (UTC)

I don't completely agree with RevRagnarok about the style. I cant understand how adding extra words to your code makes it "cleaner and easier to debug". It is the same code, with the same functionality, isn't it? On the contrary, when I review code from designers, I see the optional stuff in jr. engineers code, while the more experienced ones strictly avoid them. VHDL is verbose enough as it is, why do you want to make it even more verbose? Maybe at the end of the day, this is a matter of taste. In that case, I don't think you should force your style on people. Think if someone changed all C code on wikipedia from GNU to K&R indentation :(

Of course, there are situations such as port-mapping where the shorter style is unsafe. I agree with you on this one but this is because it can produce bad code, its not a matter of style anymore.

Also, about the examples... I took some time to synthesize every design with Synplify and check the result. They are all ok. But maybe we should create a new page that compares different HDLs (VHDL, verilog etc) instead? leave some basic stuff here and more the rest of the examples to this new page? 83.254.148.19 22:38, 13 December 2006 (UTC)

TODO List

After some preliminary comparisons of VHDL and Verilog, I think really the biggest difference is the type system.

• Complete (complex) type system in VHDL
• Only language defined types in Verilog

Actually that is one (only?) reason why one might argue that VHDL is superior to Verilog. Even when you write code which is intended for synthesis, I think the lack of a type system in Verilog is severe.

For example: If you build several modules which all connect to the same type of "command bus", you can specify the signals for the command bus in a "record" composite type in VHDL. Then each module gets an input signal of this composite type and that's it.

If you then later change the exact way the command bus works you can simply modify the type definition for the command bus instead of editing each and every module. Of course you might be able to do the same in Verilog by extensively using "include" directives, but this seems to be really ugly...