Delta delay

From Wikipedia, the free encyclopedia

This is an old revision of this page, as edited by BattyBot (talk | contribs) at 20:10, 8 October 2018 (→‎top: Removed Template:Multiple issues and General fixes). The present address (URL) is a permanent link to this revision, which may differ significantly from the current revision.

In VHDL simulations, all signal assignments occur with some infinitesimal delay, known as delta delay.[1] Technically, delta delay is of no measurable unit, but from a hardware design perspective one should think of delta delay as being the smallest time unit one could measure, such as a femtosecond (fs).

References

  1. ^ Bhasker, Jayaram (1999). A Vhdl Primer. Prentice Hall PTR, 1999. pp. 31, 46. ISBN 9780130965752.