Replay system
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The replay system is a little-known subsystem within the Intel Pentium 4 processor.[1] Its primary function is to catch operations that have been mistakenly sent for execution by the processor's scheduler. Operations caught by the replay system are then re-executed in a loop until the conditions necessary for their proper execution have been fulfilled.[2]
Overview
The replay system came about as a result of Intel's quest for ever-increasing clock speeds. These higher clock speeds necessitated very lengthy pipelines (up to 31 stages in the Prescott core). Because of this, there are six stages between the scheduler and the execution units in the Prescott core. In an attempt to maintain acceptable performance, Intel engineers had to design the scheduler to be very optimistic.[2]
The scheduler in a Pentium 4 processor is so aggressive that it will send operations for execution without a guarantee that they can be successfully executed. (Among other things, the scheduler assumes all data is in level 1 "trace cache" CPU cache.) The most common reason execution fails is that the requisite data is not available, which itself is most likely due to a cache miss. When this happens, the replay system signals the scheduler to stop, then repeatedly executes the failed string of dependent operations until they have completed successfully.[2][3]
Performance considerations
Not surprisingly, in some cases the replay system can have a very bad impact on performance. Under normal circumstances, the execution units in the Pentium 4 are in use roughly 33% of the time. When the replay system is invoked, it will occupy execution units nearly every available cycle. This wastes power, which is an increasingly important architectural design metric, but poses no performance penalty because the execution units would be sitting idle anyway. However, if hyper-threading is in use, the replay system will prevent the other thread from utilizing the execution units. This is the true cause of any performance degradation concerning hyper-threading. In Prescott, the Pentium 4 gained a replay queue, which reduces the time the replay system will occupy the execution units.[2]
In other cases, where each thread is processing different types of operations, the replay system will not interfere, and a performance increase can appear. This explains why performance with hyper-threading is application-dependent.[2]
See also
- Instruction pipeline
- Speculative execution
- Out-of-order execution
- Simultaneous multithreading
- Data dependency
References
- ^ https://web.archive.org/web/20180419120455_/https://pdfs.semanticscholar.org/presentation/cfcc/9d5a7480c4ea87e77084386d74aaff9a1ee1.pdf
- ^ a b c d e Replay: Unknown Features of the NetBurst Core (2005-06-06). "Replay: Unknown Features of the NetBurst Core". X-bit labs. Archived from the original on 2014-04-08. Retrieved 2014-04-07.
- ^ Antonio Gonzalez; Fernando Latorre; Grigorios Magklis (2010-07-01). "Processor Microarchitecture: An Implementation Perspective". Books.google.com. Morgan & Claypool Publishers. Retrieved 2014-04-07.