The Muller C-element (C-gate or sometimes, Hysteresis flip-flop) is a commonly used asynchronous logic component originally devised by David E. Muller. The output of the C-element applies logical operations on the inputs and has state or logical hysteresis. When all the inputs go high, the output switches to high. It stays in this state until all the inputs go low, at which time the output switches to low. This behavior can be extended to the asymmetric C-element where some inputs only affect the operation in one of the transitions (positive or negative).
Truth table and delay assumptions
For two input signals the C-element is defined by the equation cn=ab+(a+b)cn−1, which corresponds to the following truth table.
This table can be turned into a circuit using the Karnaugh map. However, the obtained implementation is naïve, since nothing is said about delay assumptions. To understand under what conditions the obtained circuit is workable, it is necessary to do additional analysis, which reveals that
- delay1 is a propagation delay from node 1 via environment to node 3
- delay2 is a propagation delay from node 1 via internal feedback to node 3
- delay1 must be greater than delay2
Thus, the naïve implementation is correct only for slow environment.
Implementations of the C-element
Depending on the ratio between the switching speed and power consumption, the C-element can be realized as a coarse- or fine-grain circuit.
A C-element can be implemented at the gate-level in CMOS using only gates NAND, NOR and inverters. A number of such implementations have been proposed in the former Soviet Union. Note that so-called Maevsky's implementation of the C-element is loosely based on and is an improved version of. The C-element synthesized using Taxogram language is presented in . Yet another version of the C-element built on two RS latches has been derived in  using Petrify tool.
Static and semi-static embodiments
The most known realization of a static C-element is a transistor circuit of majority gate with feedback. The majority gate in turn, can be composed of AND-OR-Invert (AOI) gate and inverter. One of the most commonly used is the semi-static C-element, which stores its previous state with two cross-coupled inverters, similar to an SRAM cell. One of the inverters is weaker than the rest of the circuit, so it can be overpowered by the pull-up and pull-down networks. If both inputs are 0, then the pull-up network changes the latch's state, and the C-element outputs a 0. If both inputs are 1, then the pull-down network changes the latch's state, making the C-element output a 1. Otherwise, the input of the latch is not connected to either Vdd or ground, and so the weak inverter (drawn smaller in the diagram) dominates and the latch outputs its previous state.
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