C-element

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The Muller C-element (C-gate or sometimes, Hysteresis flip-flop) is a commonly used asynchronous logic component originally devised by David E. Muller.[1][2][3][4] The output of the C-element applies logical operations on the inputs and has state or logical hysteresis. When all the inputs go high, the output switches to high. It stays in this state until all the inputs go low, at which time the output switches to low.[5][6][7] This behavior can be extended to the asymmetric C-element where some inputs only affect the operation in one of the transitions (positive or negative).

C-element.svg

Truth table and delay assumptions[edit]

Delays in the naïve implementation and environment

For two input signals the C-element is defined by the equation cn=ab+(a+b)cn−1, which corresponds to the following truth table.

a b cn
0 0 0
0 1 cn−1
1 0 cn−1
1 1 1

This table can be turned into a circuit using the Karnaugh map. However, the obtained implementation is naïve, since nothing is said about delay assumptions. To understand under what conditions the obtained circuit is workable, it is necessary to do additional analysis, which reveals that

  • delay1 is a propagation delay from node 1 via environment to node 3
  • delay2 is a propagation delay from node 1 via internal feedback to node 3
  • delay1 must be greater than delay2

Thus, the naïve implementation is correct only for slow environment.

Implementations of the C-element[edit]

C-element proposed in SU1081801

Depending on the ratio between the switching speed and power consumption, the C-element can be realized as a coarse- or fine-grain circuit.

Gate-level implementations[edit]

A C-element can be implemented at the gate-level in CMOS using only gates NAND, NOR and inverters. A number of such implementations have been proposed in the former Soviet Union.[8][9][10][11][12] Note that so-called Maevsky's implementation of the C-element[13][14] is loosely based on[15] and is an improved version of.[16] The C-element synthesized using Taxogram language is presented in .[17] Yet another version of the C-element built on two RS latches has been derived in [18] using Petrify tool.

Static and semi-static embodiments[edit]

A static 2-input Muller C-element. Note that transistors, branched in parallel, control the feedback signal.
C element shaded2.svg

The most known realization of a static C-element is a transistor circuit of majority gate with feedback. The majority gate in turn, can be composed of AND-OR-Invert (AOI) gate and inverter.[19][20][21][22][23] One of the most commonly used is the semi-static C-element, which stores its previous state with two cross-coupled inverters, similar to an SRAM cell. One of the inverters is weaker than the rest of the circuit, so it can be overpowered by the pull-up and pull-down networks. If both inputs are 0, then the pull-up network changes the latch's state, and the C-element outputs a 0. If both inputs are 1, then the pull-down network changes the latch's state, making the C-element output a 1. Otherwise, the input of the latch is not connected to either Vdd or ground, and so the weak inverter (drawn smaller in the diagram) dominates and the latch outputs its previous state.[24][25]

References[edit]

  1. ^ D. E. Muller, W. S. Bartky, "A theory of asynchronous circuits I," Report no. 75, Digital Computer Laboratory, University of Illinois at Urbana-Champaign, 1956.
  2. ^ D. E. Muller, W. S. Bartky, "A theory of asynchronous circuits II," Report no. 78, Digital Computer Laboratory, University of Illinois at Urbana-Champaign, 1957.
  3. ^ W. S. Bartky, "A theory of asynchronous circuits III," Report no. 96, Digital Computer Laboratory, University of Illinois at Urbana-Champaign, 1960.
  4. ^ W. D. Frazer, D. E. Muller, "A method for factoring the action of asynchronous circuits," Report no. 104, Digital Computer Laboratory, University of Illinois at Urbana-Champaign, 1960.
  5. ^ W. Fleischhammer, "Improvements in or relating to asynchronous bistable trigger circuits," UK patent specification GB1199698, Jul. 22, 1970
  6. ^ M. Kuwako, T. Nanya, "Timing-reliability evaluation of asynchronous circuits based on different delay models," IEEE International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC) 1994, pp.22-31.
  7. ^ J. Cortadella, M. Kishinevsky, Tutorial: Synthesis of control circuits from STG specifications. Summer school, Lyngby, 1997
  8. ^ B. S. Tsirlin, "H flip-flop," USSR author's certificate SU1096759, Jun. 7, 1984
  9. ^ B. S. Tsirlin, "Multiple input H flip-flop," USSR author's certificate SU1162019, Jun. 15, 1985
  10. ^ G. S. Brajlovskij, L. Ya. Rozenblyum, B. S. Tsirlin, "H flip-flop," USSR author's certificate SU1277385, Jan. 15, 1986
  11. ^ B. S. Tsirlin, "H flip-flop," USSR author's certificate SU1324108, Jul. 15, 1987
  12. ^ G. S. Brajlovskij, L. Ya. Rozenblyum, B. S. Tsirlin, "H flip-flop," USSR author's certificate SU1432733, Oct, 23, 1988
  13. ^ J. A. Brzozowski, K. Raahemifar, "Testing C-elements is not elementary," Working Conference on Asynchronous Design Methodologies (ASYNC) 1995, pp. 150-159.
  14. ^ S. Golubcovs, A. Alekseyev, A. Mokhov, A. Yakovlev, "Asynchronous circuit development with Workcraft," Technical Report NCL-EECE-MSD-TR-2011-174, University of Newcastle upon Tyne, 2011
  15. ^ V. I. Varshavskij, O. V. Maevskij, Yu. V. Mamrukov, B. S. Tsirlin, "H flip-flop," USSR author's certificate SU1081801, Mar. 23, 1984
  16. ^ G. Brajlovskij, "H flip-flop," USSR author's certificate SU945960, Jul. 23, 1982
  17. ^ N. A. Starodoubtsev, S. A. Bystrov, "Monotonic behavior refinement for synthesis of two-input-gate asynchronous circuits," IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) 2004, vol. I, pp. I-521-524.
  18. ^ J. P. Murphy, "Design of latch-based C-element," Electronics Letters, vol. 48, no. 19, 2012, pp. 1190-1191
  19. ^ D. Hampel, K. Prost, and N. Scheingberg, "Threshold logic using complementary MOS device," Patent US3900742, Aug. 19, 1975.
  20. ^ D. Doman, Engineering the CMOS Library: Enhancing Digital Design Kits for Competitive Silicon. Wiley, 2012, 327p.
  21. ^ I. E. Sutherland, "Micropipelines," Communications of the ACM, vol. 32, no. 6, pp. 720-738, 1989.
  22. ^ C. H. van Berkel, "Beware the isochronic fork," Report UR 003/91, Philips Research Laboratories, 1991.
  23. ^ H. K. O. Berge, A. Hasanbegovic, S. Aunet, "Muller C-elements based on minority-3 functions for ultra low voltage supplies," 2011 IEEE 14th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) 2011, pp. 195-200.
  24. ^ A. Morgenshtein, M. Moreinis, R. Ginosar, "Asynchronous gate-diffusion-input (GDI) circuits," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.12, no.8, pp. 847-856, 2004
  25. ^ S. M. Fairbanks, "Two-stage Muller C-element," United States Patent US6281707, Aug. 28, 2001

External links[edit]