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Delays in the naive (based on Earle latch) implementation and environment
Timing diagram of a C-element and inclusive OR gate
Behavior of the environment with multiple input transitions [1] (garbage branches [2]) admissible for C-element and inadmissible for Join element

In digital computing, the Muller C-element (C-gate, hysteresis flip-flop, coincident flip-flop, or two-hand safety circuit) is a small binary logic circuit widely used in design of asynchronous circuits and systems. It outputs 0 when all inputs are 0, it outputs 1 when all inputs are 1, and it retains its output state otherwise. It was specified formally in 1955 by David E. Muller[3] and first used in ILLIAC II computer.[4] In terms of the theory of lattices, the C-element is a semimodular distributive circuit, whose operation in time is described by a Hasse diagram.[5][6][7][8] The C-element is closely related to the rendezvous[9] and join[10] elements, where an input is not allowed to change twice in succession. In some cases, when relations between delays are known, the C-element can be realized as a sum-of-product (SOP) circuit.[11][12] Earlier techniques for implementing the C-element[13][14] include Schmitt trigger,[15] Eccles-Jordan flip-flop and last moving point flip-flop.

Truth table and delay assumptions[edit]

For two input signals the C-element is defined by the equation , which corresponds to the following truth table:

0 0 0
0 1
1 0
1 1 1

This table can be turned into a circuit using the Karnaugh map. However, the obtained implementation is naive, since nothing is said about delay assumptions. To understand under what conditions the obtained circuit is workable, it is necessary to do additional analysis, which reveals that

  • delay1 is a propagation delay from node 1 via environment to node 3,
  • delay2 is a propagation delay from node 1 via internal feedback to node 3,
  • delay1 must be greater than delay2.

Thus, the naive implementation is correct only for slow environment.[16]

Implementations of the C-element[edit]

Depending on the requirements to the switching speed and power consumption, the C-element can be realized as a coarse- or fine-grain circuit. Also, one should distinguish between single-output and dual-rail[17] realizations of C-element. A dual-rail C-element can be realized on 2-input NANDs (NORs) only.[18] A single-output realization is workable if and only if:[19]

  1. The circuit, where each input of a C-element is connected through a separate inverter to its output, is semimodular relatively to the state, where all the inverters are excited.
  2. This state is live for the output gate of C-element.

Static and semistatic implementations[edit]

Static implementations of two- and three-input C-element,[20][21][22]
Semistatic implementations of two- and multiple-input C-element.[23][24][25] For a faster version see[26]

In his report[3] Muller proposed to realize C-element as a majority gate with feedback. However, to avoid hazards linked with skews of internal delays, the majority gate must have as small number of transistors as possible.[27][28] Generally, C-elements with different timing assumptions[29] can be built on AND-OR-Invert (AOI)[30][31] or its dual, OR-AND-Invert (OAI) gate[32][33] and inverter. Yet another option patented by Varshavsky et al.[34] [35] is to shunt the input signals when they are not equal each other. Being very simple, these realizations dissipate more power due to the short-circuits. Connecting an additional majority gate to the inverted output of C-element, we obtain inclusive OR (EDLINCOR) function:[36][37] . Some simple asynchronous circuits like pulse distributors[38] can be built solely on majority gates.

Semistatic C-element stores its previous state using two cross-coupled inverters, similar to an SRAM cell. One of the inverters is weaker than the rest of the circuit, so it can be overpowered by the pull-up and pull-down networks. If both inputs are 0, then the pull-up network changes the latch's state, and the C-element outputs a 0. If both inputs are 1, then the pull-down network changes the latch's state, making the C-element output a 1. Otherwise, the input of the latch is not connected to either or ground, and so the weak inverter dominates and the latch outputs its previous state. There are also versions of semistatic C-element built on devices with negative differential resistance (NDR).[39][40] NDR is usually defined for small signal, so it is difficult to expect that such a C-element will operate in full range of voltages or currents.[original research?]

Gate-level implementations[edit]

Majority-gate realization of C-element and inclusive OR gate (a); Realizations proposed by Maevsky (b), Tsirlin (c) and Murphy (d)
An STG of dual-rail C-element with 00 transit and its circuit realized only on NAND2 as a particular case of[18] considered by V.B. Marakhovsky.
David cell (a) and its fast implementations: gate-level (b) and transistor-level (c)[41]

There is a number of different single-output circuits of C-element built on logic gates.[42][43] In particular, the so-called Maevsky's implementation [44][45][46] is a semimodular, but non-distributive (OR-causal) circuit loosely based on.[47] The NAND3 gate in this circuit can be replaced by two NAND2 gates. Note that Maevsky's C-element is actually a Join element, whose input signals cannot switch twice.[44] Yet another circuit with OR-causality, which operates as a Join element.[48] A realization of C-element on two-input gates only has been proposed by Tsirlin [49] and then synthesized by Starodoubtsev et al. using Taxogram language[50] This circuit coincides with that attributed to Bartky ,[1][44] and can operate without the input latch. Note that both the Maevsky and Tsirlin circuits are based actually on so-called David cell.[51] Its fast transistor-level implementation is used in the semistatic C-element proposed.[52] Yet another semistatic circuit using pass transistors (actually MUX 2:1) has been proposed.[53] Yet another version of the C-element built on two SR-latches has been synthesized by Murphy[54] using Petrify tool. However, this circuit includes inverter connected to one of the inputs. This inverter should have small delay. However, there are realizations of RS latches that already have one inverted input, for example.[55] Some speed-independent approaches[56][57] assume that zero-delay input inverters are available on all gates, which is a violation of true speed-independence but is fairly safe in practice. Other examples of using this assumption also exist.[58]

Non-transistor implementations[edit]

Other technologies suitable for realizing asynchronous primitives including C-element, are: carbon nanotubes,[citation needed] single-electron tunneling devices,[59] quantum dots,[60] and molecular nanotechnology.[61]

Generalization for multiple-valued logic[edit]

The definition of C-element can be generalized for multiple-valued logic,[7][62][63] or even for continuous signals:

For example, the truth table for a balanced ternary C-element with two inputs is

−1 −1 −1
−1 0
−1 1
0 −1
0 0 0
0 1
1 −1
1 0
1 1 1

Since the majority gate is a particular case of threshold gate, any of known realizations of threshold gate[64] can in principle be used for building a C-element. In the multiple-valued case, however, connecting the output of majority gate to one or several inputs may have no desirable effect. For example, using the ternary majority function defined as[65]

does not lead to the ternary C-element specified by the truth table, if the sum is not split into pairs. However, even without such a splitting two ternary majority functions are suitable for building a ternary inclusive OR gate.


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