C-element

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Delays in the naive (based on Earle latch) implementation and environment
Timing diagram of a C-element and inclusive OR gate
Majority-gate realization of C-element and inclusive OR gate (a); Realizations proposed by Maevsky (b), Tsirlin (c) and Murphy (d)
Static implementations of two- and three-input C-element[1][2][3]
Semi-static implementations of two- and multiple-input C-element [4][5][6]. For a faster version see[7]
David cell (a) and its fast implementations: gate-level (b) and transistor-level (c)[8]

The Muller C-element (C-gate, hysteresis flip-flop, or sometimes coincident flip-flop, two-hand safety circuit) is a small digital block widely used in design of asynchronous circuits and systems. It has been specified formally in 1955 by David E. Muller[9] and first used in ILLIAC II computer.[10] In terms of the theory of lattices, the C-element is a semimodular distributive circuit, whose operation in time is described by a Hasse diagram.[11][12][13] The C-element is closely related to the rendezvous[14] and join[15] elements, where an input is not allowed to change twice in succession. In some cases, when relations between delays are known, the C-element can be realized as a sum-of-product (SOP) circuit [16],[17]. Earlier techniques for implementing the C-element[18][19] include Schmidt trigger,[20] Eccles-Jordan flip-flop and last moving point flip-flop.

Truth table and delay assumptions[edit]

For two input signals the C-element is defined by the equation , which corresponds to the following truth table:

0 0 0
0 1
1 0
1 1 1

This table can be turned into a circuit using the Karnaugh map. However, the obtained implementation is naive, since nothing is said about delay assumptions. To understand under what conditions the obtained circuit is workable, it is necessary to do additional analysis, which reveals that

  • delay1 is a propagation delay from node 1 via environment to node 3,
  • delay2 is a propagation delay from node 1 via internal feedback to node 3,
  • delay1 must be greater than delay2.

Thus, the naive implementation is correct only for slow environment.[21]

Note that the definition of C-element can be easily generalized for multiple-valued logic or even for continuous signals:

For example, the truth table for a balanced ternary C-element with two inputs is

−1 −1 −1
−1 0
−1 1
0 −1
0 0 0
0 1
1 −1
1 0
1 1 1

Implementations of the C-element[edit]

Depending on the requirements to the switching speed and power consumption, the C-element can be realized as a coarse- or fine-grain circuit. Also, one should distinguish between single-output and differential[22] realizations of C-element. Differential realization is possible using only NANDs (only NORs). A single-output realization is workable if and only if:[23]

  1. The circuit, where each input of a C-element is connected through a separate inverter to its output, is semimodular relatively to the state, where all the inverters are excited.
  2. This state is live for the output gate of C-element.

Gate-level implementations[edit]

There is a number of different single-output circuits of C-element built on logic gates[24][25]. In particular, the so-called Maevsky's implementation[26][27][28] is a non-distributive circuit loosely based on[29]. Non-distributivity is introduced sometimes to increase concurrency. The 3NAND gate in this circuit can be replaced by two 2NAND gates. The C-element using only two-input gates has been proposed by Tsirlin[30] and then synthesized by Starodoubtsev et al. using Taxogram language [31] This circuit coincides with that attributed (without reference) to Bartky [26] and can operate without the input latch. Yet another version of the C-element built on two RS latches has been synthesized by Murphy[32] using Petrify tool. However, this circuit includes inverter connected to one if the inputs. This inverter should have small delay. However, there are realizations of RS latches that already have one inverted input, for example [33]. Note that some speed-independent approaches [34][35] assume that zero-delay input inverters are available on all gates, which is a violation of true speed-independence but is fairly safe in practice. Other examples of using this assumption also exist.[36]

Static and semistatic implementations[edit]

In his report[9] Muller proposed to realize C-element as a majority gate with feedback. However, to avoid hazards linked with skews of internal delays, the majority gate must have as small number of transistors as possible.[37][38] Generally, C-elements with different timing assumptions[39] can be built on AND-OR-Invert (AOI)[40][41] or its dual, OR-AND-Invert (OAI) gate[42][43] and inverter. Yet another option patented by Varshavsky et al.[44] [45] is to shunt the input signals when they are not equal each other. Being very simple, these realizations dissipate more power due to the short-circuits. Note that connecting an additional majority gate to the inverted output of C-element, we obtain inclusive OR (EDLINCOR) function:[46][47] . Note also that some simple asynchronous circuits like pulse distributors[48] can be built solely on majority gates.

Semistatic C-element stores its previous state using two cross-coupled inverters, similar to an SRAM cell. One of the inverters is weaker than the rest of the circuit, so it can be overpowered by the pull-up and pull-down networks. If both inputs are 0, then the pull-up network changes the latch's state, and the C-element outputs a 0. If both inputs are 1, then the pull-down network changes the latch's state, making the C-element output a 1. Otherwise, the input of the latch is not connected to either or ground, and so the weak inverter dominates and the latch outputs its previous state. There are also versions of semistatic C-element built on devices with negative differential resistance (NDR).[49][50] It should be noted however, that NDR is usually defined for small signal. So, it is difficult to expect that such a C-element will operate in full range of voltages or currents.

Generalizations and non-transistor implementations[edit]

Since the majority gate is a particular case of threshold gate, any of known realizations of threshold gate[51] can in principle be used for building a C-element. In the multiple-valued case, however, connecting the output of majority gate to one or several inputs may have no desirable effect. For example, using the ternary majority function defined as[52]

does not lead to the ternary C-element specified by the truth table, if the sum is not split into pairs. However, even without such a splitting two ternary majority functions are suitable for building a ternary inclusive OR gate. Note that both the Maevsky and Tsirlin circuits are based actually on so-called David cell.[53] Its fast transistor-level implementation is used in the semistatic C-element proposed.[54] Yet another semistatic circuit using pass transistors (actually MUX 2:1) has been proposed.[55] Other technologies suitable for realizing asynchronous primitives including C-element, are: carbon nanotubes[56], single-electron tunneling devices[57], quantum dots[58], and molecular nanotechnology[59].

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