Common Electrical I/O
The Common Electrical I/O (CEI) refers to a series of influential Interoperability Agreements (IAs) that have been published by the Optical Internetworking Forum (OIF). CEI defines the electrical and jitter requirements for 3.125, 6, 11, 25-28, and 56 Gbit/s electrical interfaces.
CEI, the Common Electrical I/O
The Common Electrical I/O (CEI) Interoperability Agreement published by the OIF defines the electrical and jitter requirements for 3.125, 6, 11, 25-28, and 56 Gbit/s SerDes interfaces. This CEI specification has defined SerDes interfaces for the industry since 2004, and it has been highly influential. The development of electrical interfaces at the OIF began with SPI-3 in 2000, and the first differential interface was published in 2003. The seventh generation electrical interface, CEI-56G, defines five reaches of 56 Gb/s interfaces. The OIF began work on its eighth generation with its CEI-112G project.[1] CEI has influenced or has been adopted or adapted in many other serial interface standards by many different standards organizations over its long lifetime. SerDes interfaces have been developed based on CEI for most ASIC and FPGA products.
CEI direct predecessors
Throughout the 2000's, the OIF produced an important series of interfaces that influenced the development of multiple generations of devices. Beginning with the donation of the PL-3 interface by PMC-Sierra in 2000, the OIF produced the System Packet Interface (SPI) family of packet interfaces. SPI-3 and SPI-4.2 defined two generations of devices before they were supplanted by the closely related Interlaken standard in the SPI-5 generation in 2006.
The OIF also defined the SerDes Framer Interface (SFI) family of specifications in parallel with SPI. As a part of the SPI-5 and SFI-5 development, a common electrical interface was developed termed SxI-5. SxI-5 abstracted the electrical I/O interface away from the individual SPI and SFI documents. This abstraction laid the groundwork for the highly successful CEI family of Interoperability Agreements and was incorporated in the original release of CEI 1.0 a generation later.
Generations of OIF Electrical Interfaces
Gen. |
IA Title |
Pub. as |
Clause #'s |
Max per pair |
Mult. of bit rate per wire |
Typical appli -cation |
Year pub. |
Adopted, adapted or influenced |
Num. ranges |
Modu- lations | |
|---|---|---|---|---|---|---|---|---|---|---|---|
| 8 | CEI-112G | Presumably CEI 5.0 | 116 Gbit/s | 580x | 800GE thru 100GE | (started in 2016) | 5 | ||||
| 7 | CEI-56G | CEI 4.0[2][3] | 16-22 | 58 Gbit/s | 290x | 400GE thru 50GE | 2017 | IEEE 802.3bs and 802.3cd, Infiniband HDR, 64G Fibre Channel | 5 | NRZ, PAM-4 and ENRZ | |
| 6.5 | CEI-28G (added 25G LR) | CEI 3.1 [4] | 11 | 28 Gbit/s (25 for LR) | 140x | 100GE thru 25GE | 2011 | InfiniBand EDR, 32G Fibre Channel, SATA 3.2, IEEE 802.3 100GBASE-KR4, 100GBASE-CR4 and CAUI4, SAS-4, Interlaken 1.9 | 4 | NRZ | |
| 6 | CEI-28G | CEI 3.0,[5] | 10, 12-14 | 28 Gbit/s | 140x | 100GE thru 25GE | 2008 | InfiniBand EDR, 32GFC, SATA 3.2, IEEE 802.3 CAUI4, SAS-4, Interlaken 1.9 | 4 | NRZ | |
| 5 | CEI-11G | CEI 2.0 | 8-9 | 11 Gbit/s | 55x | OC-768, 100GE, 40GE | 2008 | InfiniBand QDR, 10GBASE-KR, 10GFC, 16GFC, SAS-3, RapidIO v3, Interlaken | 3 | NRZ | |
| 4 | CEI-6G | CEI 1.0 | 6-7 | 6 Gbit/s | 30x | OC-768 (~40 Gbit/s) | 2004 | 4GFC, 8GFC, InfiniBand DDR, SATA 3.0, SAS-2, RapidIO v2, HyperTransport 3.1, Interlaken | 2 | NRZ | |
| 3 | SxI-5 | SxI-5 [6] and CEI 1.0 | 4-5 | 3.125 Gbit/s | 16x | OC-192, 10GE | 2002, 2004 | Interlaken, SPI-5, SFI-5, FC 2G, InfiniBand SDR, XAUI, 10GBASE-KX4, 10GBASE-CX4, SATA 2.0, SAS-1, RapidIO v1 | 1 | NRZ | |
| 2 | SPI-4.2 | SPI-4, 4.2 [7] | 0.8 Gbit/s | 4x | OC-48 (2.488 Gbit/s) | 2001-2 | HyperTransport 1.03 | 1 | NRZ | ||
| 1 | SPI-3 | SPI-3 | 0.1 Gbit/s (single ended) | 1 (ref) | OC-12 (0.622 Gbit/s) | 2000 | (From PMC-Sierra's PL-3) | 1 | NRZ |
Two earlier generations in this development path were defined by some of the same individuals at the ATM Forum in 1994 and 1995. These specifications were called UTOPIA Level 1 and 2. These operated at 25 Mbit/s (0.025 Gbit/s) and 50 Mbit/s per wire single ended and were used in OC-3 (155 Mbit/s) applications.[8] PL-3 was a packet extension of the cells carried by those earlier interfaces.
Public demonstrations
Compliant implementations to the draft CEI-56G IAs were demonstrated in the OIF booth at the Optical Fiber Conference in 2015, 2016 and 2017.[9]
References
- ^ "OIF Launches CEI-112G Project for 100G Serial Electrical Links". Businesswire, 30 Aug 2016.
- ^ "Common Electrical I/O (CEI) - Electrical and Jitter Interoperability agreements for 6G+ bps, 11G+ bps, 25G+, and 56G+ bps I/O" (PDF). OIF, Dec 2017.
- ^ "OIF CEI Technology For 56 Gbps Available For Wider Industry Adoption". OIF, Jan 2018.
- ^ "Common Electrical I/O (CEI) - Electrical and Jitter Interoperability agreements for 6G+ bps, 11G+ bps and 25G+ bps I/O" (PDF). OIF, 8 Feb 2014.
- ^ "Common Electrical I/O (CEI) - Electrical and Jitter Interoperability agreements for 6G+ bps, 11G+ bps and 25G+ bps I/O" (PDF). OIF, Sept 2011.
- ^ "System Interface Level 5 (SxI-5): Common Electrical Characteristics for 2.488 – 3.125Gbps Parallel Interfaces" (PDF). OIF, Oct 2005.
- ^ "System Packet Interface Level 4 (SPI-4) Phase 2 Revision 1: OC-192 System Interface for Physical and Link Layer Devices" (PDF). OIF, 15 Oct 2003.
- ^ "OIF shows 56G electrical interfaces & CFP2-ACO". Gazzettabyte, 25 Mar 2015.
- ^ "ATM Physical Layers" (PDF). Washington University at St. Louis (originally published by Ohio State), ~1998.