It was invented by Cisco Systems and Cortina Systems in 2006, optimized for high-bandwidth and reliable packet transfers. It builds on the channelization and per channel flow control features of SPI-4.2, while reducing the number of integrated circuit (chip) I/O pins by using high speed SerDes technology. Bundles of serial links create a logical connection between components with multiple channels, backpressure capability, and data-integrity protection to boost the performance of communications equipment. Interlaken manages speeds of up to 6 Gbit/s per pin (lane) and large numbers of lanes can form an Interlaken interface. It was designed to handle high-speed (10 Gigabit Ethernet, 100 Gigabit Ethernet and beyond) computer network connections.
An alliance was formed in 2007.
- "Cisco Systems, Cortina Systems Announce Interlaken Protocol". News release. Cisco Systems Inc. April 24, 2006. Retrieved June 16, 2011.
- "Interlaken Alliance". official web site. Retrieved June 16, 2011.
- Interlaken White Paper 2007
- Altera, Sarance Technologies and Cortina Systems Join Forces on First Interlaken Protocol IP Core for FPGAs
- SLE Introduces Interlaken Interconnect Protocol IP Core
- Open-Silicon Interlaken IP
- EE Times - Open-Silicon updates 'Interlaken' IP core
- Open-Silicon Enhances its Interlaken IP Core For Very High-Speed Chip-to-Chip Serial Interfaces
- Open-Silicon Secures 20th Interlaken IP License
- Open-Silicon’s Interlaken IP Core Chosen for ALAXALA’s Advanced Networking Infrastructure Device
- Open-Silicon’s Configurable Interlaken IP Core Delivers High-Performance Chip to Chip Interface for Networking Products at 28nm Process Node
- Open-Silicon Unveils Interlaken IP Core with 600 Gbps Chip-to-Chip Interface Support for Networking, Storage and High-Performance Computing Products
- Open-Silicon’s Interlaken IP Core Selected for Netronome’s Next-Generation Flow Processors
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