Intel Paragon

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An experimental Touchstone Delta (1990) built at Caltech
Intel Paragon XP/S (1992) at Computer History Museum
Intel Paragon XP/E (1993) single cabinet system Cats

The Intel Paragon is a discontinued series of massively parallel supercomputers that was produced by Intel in the 1990s. The Paragon XP/S is a productized version of the experimental Touchstone Delta system that was built at Caltech, launched in 1992. The Paragon superseded Intel's earlier iPSC/860 system, to which it is closely related.

The Paragon series is based on the Intel i860 RISC microprocessor. Up to 2048 (later, up to 4096) i860s are connected in a 2D grid. In 1993, an entry-level Paragon XP/E variant was announced with up to 32 compute nodes.

Mesh interconnect on XP/E cabinet

The system architecture is a partitioned system, with the majority of the system comprising diskless compute nodes and a small number of I/O nodes interactive service nodes. Since the bulk of the nodes have no permanent storage, it is possible to "Red/Black switch" the compute partition from classified to unclassified by disconnecting one set of I/O nodes with classified disks and then connecting an unclassified I/O partition.

Intel intended the Paragon to run the OSF/1 AD distributed operating system on all processors. However, this was found to be inefficient in practice, and a light-weight kernel called SUNMOS was developed at Sandia National Laboratories to replace OSF/1 AD on the Paragon's compute processors.

Oak Ridge National Laboratory operated a Paragon XP/S 150 MP, one of the largest Paragon systems, for several years.

The prototype for the Intel Paragon was the Intel Delta, built by Intel with funding from DARPA and installed operationally at the California Institute of Technology in the late 1980s with funding from the National Science Foundation. The Delta was one of the few computers to sit significantly above the curve of Moore's Law.

Compute nodes[edit]

The computer boards was produced in two variants: the GP16 with 16 MB of memory and two CPUs, and the MP16 with three CPUs. Each node has a B-NIC interface that connects to the mesh routers on the backplane. The compute nodes are diskless and performed all I/O over the mesh. During system software development, a light-pen was duct-taped to the status LED on one board and a timer interrupt was used to bit bang a serial port.

The B-NIC ASIC is the square chip with the circular heat-sink.

I/O nodes[edit]

The IO boards have either SCSI drive interfaces or HiPPI network connections and are used to provide data to the compute nodes. They do not run any user applications. The MP64 I/O node has three i860 CPUs and an i960 CPU used in the disk controller.


  • "Intel Paragon Installed at Caltech". Retrieved November 25, 2015.
  • Esser, R.; Knecht, R. (1993). "Intel Paragon XP/S — Architecture and Software Environment". In Meuer, H.W. (ed.). Supercomputer '93. Informatik aktuell. Springer. pp. 121–141. doi:10.1007/978-3-642-78348-7_13. ISBN 978-3-642-78348-7.

External Links[edit]

Preceded by
Numerical Wind Tunnel
124.0 gigaflops
World's most powerful supercomputer
June 1994
Succeeded by
Numerical Wind Tunnel
170.0 gigaflops