Interrupt request

The computing phrase "interrupt request" (or IRQ) is used to refer to either the act of interrupting the bus lines used to signal an interrupt, or the interrupt input lines on a Programmable Interrupt Controller (PIC). The interrupt request level (IRQL) is the priority of an interrupt request.

Interrupt lines are often identified by an index with the format of IRQ followed by a number. For example, on the Intel 8259 family of PICs there are eight interrupt inputs commonly referred to as IRQ0 through IRQ7. In x86 based computer systems that use two of these PICs, the combined set of lines are referred to as IRQ0 through IRQ15. Technically these lines are named IR0 through IR7, and the lines on the ISA bus to which they were historically attached are named IRQ0 through IRQ15

Newer x86 systems integrate an Advanced Programmable Interrupt Controller (APIC) that conforms to the Intel APIC Architecture. These APICs support a programming interface for up to 255 physical hardware IRQ lines per APIC, with a typical system implementing support for only around 24 total hardware lines.

Overview

When working with computer hardware, installing and removing devices, the system relies on interrupt requests. There are default settings that are configured in the system BIOS and recognized by the operating system. These default settings can be altered by advanced users. Modern plug and play technology has not only reduced the need for concern for these settings, but has virtually eliminated manual configuration.

x86 IRQs

See Intel 8259 for a common list and discussion of hardware IRQ lines in x86 systems.

Typically, on systems using the Intel 8259, 16 IRQs are used. IRQs 0 to 7 are managed by one Intel 8259 PIC, and IRQs 8 to 15 by a second Intel 8259 PIC. The first PIC, the master, is the only one that directly signals the CPU. The second PIC, the slave, instead signals to the master on its IRQ 2 line, and the master passes the signal on to the CPU. There are therefore only 15 interrupt request lines available for hardware.

On newer systems using the Intel APIC Architecture, typically there are 24 IRQs available, and the extra 8 IRQs are used to route PCI interrupts, avoiding conflict between dynamically configured PCI interrupts and statically configured ISA interrupts. On early APIC systems with only 16 IRQs or with only Intel 8259 interrupt controllers, PCI interrupt lines were routed to the 16 IRQs using a PIR integrated into the southbridge.

The easiest way of viewing this information on Microsoft Windows is to use Device Manager or System Information (msinfo32.exe). On Linux, IRQ mappings can be viewed by executing cat /proc/interrupts or procinfo programs.

Master PIC

IRQ 0 — system timer (cannot be changed);
IRQ 1 — keyboard controller (cannot be changed);
IRQ 2 — cascaded signals from IRQs 8–15;
— any devices configured to use IRQ 2 will actually be using IRQ 9
IRQ 3 — serial port controller for COM2 (shared with COM4, if present);
IRQ 4 — serial port controller for COM1 (shared with COM3, if present);
IRQ 5 — LPT port 2 or sound card;
IRQ 6 — floppy disk controller;
IRQ 7 — LPT port 1 or sound card (8-bit Sound Blaster and compatibles).

Slave PIC

IRQ 8 — real-time clock;
IRQ 9 — open interrupt / available or SCSI host adapter;
— any devices configured to use IRQ 2 will actually be using IRQ 9
IRQ 10 — open interrupt / available or SCSI or NIC;
IRQ 11 — open interrupt / available or SCSI or NIC;
IRQ 12 — mouse on PS/2 connector;
IRQ 13 — math co-processor or integrated floating point unit or inter-processor interrupt (use depends on OS);
IRQ 14 — primary ATA channel;
IRQ 15 — secondary ATA channel
ATA interface usually serves hard disks and CD drives

More information

More information on the Intel 8259 PIC and its IRQ lines can be found in the IA-32 Intel Architecture Software Developer’s Manual, Volume 3A: System Programming Guide, Part 1, freely available on the Intel website.

Ralf Brown's Interrupt List

References

Gilluwe, Frank van. The Undocumented PC, Second Edition, Addison-Wesley Developers Press, 1997. ISBN 0-201-47950-8
Shanley, Tom. ISA System Architecture, Third Edition, Addison-Wesley Publishing Company, 1995. ISBN 0-201-40996-8
Solari, Edward. PCI & PCI-X Hardware and Software Architecture & Design, Sixth Edition, Research Tech Inc., 2004. ISBN 0-9760865-0-6