# Iron law of processor performance

In computer architecture, the iron law of processor performance (or simply iron law of performance) describes the performance trade-off between complexity and the number of primitive instructions that processors use to perform calculations.[1] This formulation of the trade-off spurred the development[citation needed] of Reduced Instruction Set Computers (RISC) whose instruction set architectures (ISAs) leverage a smaller set of core instructions to improve performance. The term was coined by Douglas Clark[2] based on research performed by Clark and Joel Emer in the 1980s.[3]

## Explanation

The performance of a processor is the time it takes to execute a program: ${\displaystyle {\tfrac {Time}{Program}}}$. This can be further broken down into three factors:[4]

${\displaystyle {\frac {Instructions}{Program}}\times {\frac {ClockCycles}{Instruction}}\times {\frac {Time}{ClockCycles}}}$
Selection of an instruction set architecture affects ${\displaystyle {\tfrac {Instructions}{Program}}\times {\tfrac {ClockCycles}{Instruction}}}$, whereas ${\displaystyle {\tfrac {Time}{ClockCycles}}}$ is largely determined by the manufacturing technology. Classic Complex Instruction Set Computer (CISC) ISAs optimized ${\displaystyle {\tfrac {Instructions}{Program}}}$ by providing a larger set of more complex CPU instructions. Generally speaking, however, complex instructions inflate the number of clock cycles per instruction (${\displaystyle {\tfrac {ClockCycles}{Instruction}}}$) because they must be decoded into simpler micro-operations actually performed by the hardware. After converting X86 binary to the micro-operations used internally, the total number of operations is close to what is produced for a comparable RISC ISA.[5]

The iron law of processor performance makes this trade-off explicit and pushes for optimization of ${\displaystyle {\tfrac {Time}{Program}}}$as a whole, not just a single component. While the iron law is credited for sparking the development of RISC architectures,[citation needed] it does not imply that a simpler ISA is always faster. If that were the case, the fastest ISA would consist of simple binary logic. A single CISC instruction can be faster than the equivalent set of RISC instructions when it enables multiple micro-operations to be performed in a single clock cycle. CISC processors can also achieve higher performance using techniques such as modular extensions, predictive logic, compressed instructions, and macro-operation fusion.[6][5][7]