Iron law of processor performance

From Wikipedia, the free encyclopedia
Jump to navigation Jump to search

In computer architecture, the iron law of processor performance (or simply iron law of performance) describes the performance trade-off between complexity and the number of primitive instructions that processors use to perform calculations.[1] This formulation of the trade-off spurred the development[citation needed] of Reduced Instruction Set Computers (RISC) whose instruction set architectures (ISAs) leverage a smaller set of core instructions to improve performance. The term was coined by Douglas Clark[2] based on research performed by Clark and Joel Emer in the 1980s.[3]


The performance of a processor is the time it takes to execute a program: . This can be further broken down into three factors:[4]

Selection of an instruction set architecture affects , whereas is largely determined by the manufacturing technology. Classic Complex Instruction Set Computer (CISC) ISAs optimized by providing a larger set of more complex CPU instructions. Generally speaking, however, complex instructions inflate the number of clock cycles per instruction () because they must be decoded into simpler micro-operations actually performed by the hardware. After converting X86 binary to the micro-operations used internally, the total number of operations is close to what is produced for a comparable RISC ISA.[5]

The iron law of processor performance makes this trade-off explicit and pushes for optimization of as a whole, not just a single component. While the iron law is credited for sparking the development of RISC architectures,[citation needed] it does not imply that a simpler ISA is always faster. If that were the case, the fastest ISA would consist of simple binary logic. A single CISC instruction can be faster than the equivalent set of RISC instructions when it enables multiple micro-operations to be performed in a single clock cycle. CISC processors can also achieve higher performance using techniques such as modular extensions, predictive logic, compressed instructions, and macro-operation fusion.[6][5][7]

See also[edit]


  1. ^ Eeckhout, Lieven (2010). Computer Architecture Performance Evaluation Methods. Morgan & Claypool. pp. 5–6. ISBN 9781608454679. Retrieved 9 March 2021.
  2. ^ Joel, Emer (2021-04-13), YArch 2021 Keynote, retrieved 2021-09-02
  3. ^ A Characterization of Processor Performance in the VAX-11/780, Joel S. Emer, Douglas W. Clark, 1984, IEEE
  4. ^ Asanovic, Krste (2019). "Lecture 4 - Pipelining" (PDF). Department of Electrical Engineering and Computer Sciences at UC Berkeley (Lecture Slides). p. 2. Archived from the original on 2020-03-11. Retrieved 2020-03-11.
  5. ^ a b Celio, Christopher; Dabbelt, Palmer; Patterson, David A.; Asanović, Krste (2016-07-08). "The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V". arXiv:1607.02318 [cs.AR].
  6. ^ Engheim, Erik (2020-12-28). "The Genius of RISC-V Microprocessors". Medium. Retrieved 2021-03-11.
  7. ^ Celio, Christopher (2016-07-26), A Comparison of RISC V, ARM, and x86, retrieved 2021-03-11