Negative-bias temperature instability

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Negative-bias temperature instability (NBTI) is a key reliability issue in MOSFETs. NBTI manifests as an increase in the threshold voltage and consequent decrease in drain current and transconductance of a MOSFET. The degradation exhibits logarithmic dependence on time. It is of immediate concern in p-channel MOS devices, since they almost always operate with negative gate-to-source voltage; however, the very same mechanism also affects nMOS transistors when biased in the accumulation regime, i.e. with a negative bias applied to the gate.


In sub-micrometer devices nitrogen is incorporated into the silicon gate oxide to reduce the gate leakage current density and prevent boron penetration. However, incorporating nitrogen enhances NBTI.[why?] For new technologies (32 nm and shorter nominal channel lengths), high-K metal gate stacks are used as an alternative to improve the gate current density for a given equivalent oxide thickness (EOT). Even with the introduction of new materials like hafnium oxides, NBTI remains.

It is possible that the interfacial layer composed of nitrided silicon dioxide is responsible for those instabilities. This interfacial layer results from the spontaneous oxidation of the silicon substrate when the high-K dielectric is deposited. To limit this oxidation, the silicon interface is saturated with N resulting in a very thin and nitrided oxide layer.

It is commonly accepted that two kinds of trap contribute to NBTI:

  • first, interface traps are generated. Those traps cannot be recovered over a reasonable time of operation. Some authors refer to them as permanent traps. Those traps are the same as the one created by channel hot carrier. In the case of NBTI, it is believed that the electric field is able to break Si–H bonds located at the Silicon-oxide interface. H is released in the substrate where it migrates. The remaining dangling bond Si- (Pb center) contribute to the threshold voltage degradation.
  • on top of the interface states generation some preexisting traps located in the bulk of the dielectric (and supposedly nitrogen related), are filled with holes coming from the channel of pMOS. Those traps can be emptied when the stress voltage is removed. This Vth degradation can be recovered over time.

The existence of two coexisting mechanisms created a large controversy, with the main controversial point being about the recoverable aspect of interface traps. Some authors suggest that only interface traps are generated and recovered; today this hypothesis is ruled out.[citation needed] The situation is clearer but not completely solved. Some authors suggest that interface traps generation is responsible for hole trapping in the bulk of dielectrics. A tight coupling between two mechanism may exist but nothing is demonstrated clearly.

With the introduction of high K metal gates, a new degradation mechanism appeared. The PBTI for positive bias temperature instabilities affects nMOS transistor when positively biased. In this particular case, no interface states are generated and 100% of the Vth degradation may be recovered. Those results suggest that there is no need to have interface state generation to trapped carrier in the bulk of the dielectric.

See also[edit]


  • Dieter K. Schroder and Jeff A. Babcock, “Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing”, Journal of applied Physics, vol. 94, pp. 1–18, July 2003.
  • M. Alam and S. Mahapatra, “A comprehensive model of PMOS NBTI degradation”, Microelectronics Reliability, vol. 45, no. 1, pp. 71–81, Jan. 2005.
  • D.K. Schroder, "Negative bias temperature instability: What do we understand?," Microelectronics Reliability, vol. 47, pp. 841–852, June 2007.