Qualcomm Hexagon

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Hexagon
DesignerQualcomm
Bits32-bit
Introduced2006 (QDSP6)
Design4-way multithreaded VLIW
TypeRegister-Register
EncodingFixed 4 byte per instruction, up to 4 instructions in VLIW multiinstruction
OpenProprietary
Registers
General purpose32-bit GPR: 32, can be paired to 64-bit[1]

About Qualcomm Hexagon[edit]

Hexagon is the brand name for a family of digital signal processor (DSP) products from Qualcomm. Hexagon is also known as QDSP6, standing for “sixth generation digital signal processor.” According to Qualcomm, the Hexagon architecture is designed to deliver performance with low power over a variety of applications.:[2][3]

Each version of Hexagon has an instruction set and a micro-architecture. These two features are intimately related.

Hexagon is used in Qualcomm Snapdragon chips, for example in smartphones, cars, wearable devices and other mobile devices and is also used in components of cellular phone networks.

Digital Signal Processing[edit]

A DSP is a chip or chip component that carries out specialized data processing to encode, decode, transmit, compress or otherwise transform streams of samples such as audio and speech, sonar, radar, other sensor data, images and computer graphics, medical and other telemetry, industrial controls system data, seismology data and other signals. The essential feature of signals is that at some point a digital component repeatedly, periodically, measures something and produces a set of bits which encodes the measurement value. The period may be nanoseconds, microseconds, milliseconds or longer. DSPs can include codecs which compress and decompress video data streams, Fast Fourier Transforms and many other capabilities.

Signal processing is used in gaming, cryptography (secure transmission of secret data) and telephony as well as applications of artificial intelligence such as image recognition.

Instruction Set Architecture[edit]

Computing devices have instruction sets, which are their lowest, most primitive languages. Common instructions are those which cause two numbers to be added, multiplied or combined in other ways, as well as instructions that direct the processor where to look in memory for its next instruction. There are many other types of instructions.

Assemblers and compilers that translate computer programs into streams of instructions – bit streams - that the device can understand and carry out (execute). As an instruction stream executes, the integrity of system function is supported by the use of instruction privilege levels. Privileged instructions have access to more resources in the device, including memory. Hexagon supports privilege levels.

Originally, Hexagon instructions operated on integer numbers but not floating point numbers,[4] but in v5 floating point support was added.[5]

The processing unit which handles execution of instructions is capable of in-order dispatching up to 4 instructions (the packet) to 4 Execution Units every clock. Hardware multi-threading is implemented as barrel temporal multi-threading - threads are switched in round-robin fashion each cycle, so the 600 MHz physical core is presented as three logical 200 MHz cores before V5. Hexagon V5 switched to dynamic multi-threading (DMT) with thread switch on level two cache misses, interrupt waiting or on special instructions.

Micro-architecture[edit]

Micro-architecture is the physical structure of a chip or chip component that makes it possible for a device to carry out the instructions. A given instruction set can be implemented by a variety of micro-architectures. The buses – data transfer channels – for Hexagon devices are 32 bits wide. That is, 32 bits of data can be moved from one part of the chip to another in a single step. The Hexagon micro-architecture is multi-threaded,[6] which means that it can simultaneously process more than one stream of instructions, enhancing data processing speed. Hexagon supports very long instruction words,[7][8] which are groupings of four instructions that can be executed “in parallel.” Parallel execution means that multiple instructions can run simultaneously without one instruction having to complete before the next one starts. The Hexagon micro-architecture supports single instruction, multiple data operations,[9] which means that a when a Hexagon device receives an instruction it can carry out the operation on more than one piece of data at the same time

According to 2012 estimation, Qualcomm shipped 1.2 billion DSP cores inside its system on a chip (SoCs) (average 2.3 DSP core per SoC) in 2011, and 1.5 billion cores were planned for 2012, making the QDSP6 the most shipped architecture of DSP[10] (CEVA had around 1 billion of DSP cores shipped in 2011 with 90% of IP-licenseable DSP market[11]).

The Hexagon architecture is designed to deliver performance with low power over a variety of applications. It has features such as hardware assisted multithreading, privilege levels, Very Long Instruction Word (VLIW), Single Instruction Multiple Data (SIMD),[12][13] and instructions geared toward efficient signal processing. The CPU is capable of in-order dispatching up to 4 instructions (the packet) to 4 Execution Units every clock.[14][15] Hardware multithreading is implemented as barrel temporal multithreading - threads are switched in round-robin fashion each cycle, so the 600 MHz physical core is presented as three logical 200 MHz cores before V5.[16][17] Hexagon V5 switched to dynamic multithreading (DMT) with thread switch on L2 misses, interrupt waiting or on special instructions.[17][18]

At Hot Chips 2013 Qualcomm announced details of their Hexagon 680 DSP. Qualcomm announced Hexagon Vector Extensions (HVX). HVX is designed to allow significant compute workloads for advanced imaging and computer vision to be processed on the DSP instead of the CPU.[19] In March 2015 Qualcomm announced their Snapdragon Neural Processing Engine SDK which allow AI acceleration using the CPU, GPU and Hexagon DSP.[20]

Qualcomm's Snapdragon 855 contains their 4th generation on-device AI engine, which includes the Hexagon 690 DSP and Hexagon Tensor Accelerator (HTA) for AI acceleration.[21]

Software support[edit]

Operating systems[edit]

The port of Linux for Hexagon runs under a hypervisor layer ("Hexagon Virtual Machine"[22]) and was merged with the 3.2 release of the kernel.[23][24] The original hypervisor is closed-source, and in April 2013 a minimal open-source hypervisor implementation for QDSP6 V2 and V3, the "Hexagon MiniVM" was released by Qualcomm under a BSD-style license.[25][26]

Compilers[edit]

Support for Hexagon was added in 3.1 release of LLVM by Tony Linthicum.[27] Hexagon/HVX V66 ISA support was added in 8.0.0 release of LLVM.[28] There is also a non-FSF maintained branch of GCC and binutils.[29]

Adoption of the SIP block[edit]

Qualcomm Hexagon DSPs have been available in Qualcomm Snapdragon SoC since 2006.[30][31] In Snapdragon S4 (MSM8960 and newer) there are three QDSP cores, two in the Modem subsystem and one Hexagon core in the Multimedia subsystem. Modem cores are programmed by Qualcomm only, and only Multimedia core is allowed to be programmed by user.

They are also used in some femtocell processors of Qualcomm, including FSM98xx, FSM99xx and FSM90xx.[32]

Third-party integration[edit]

In March 2016, it was announced that semiconductor company Conexant's AudioSmart audio processing software was being integrated into Qualcomm's Hexagon.[33]


In May 2018 wolfSSL added support for using Qualcomm Hexagon. [34] This is support for running wolfSSL crypto operations on the DSP. In addition to use of crypto operations a specialized operation load management library was later added.

Versions[edit]

There are six versions of QDSP6 architecture released: V1 (2006), V2 (2007–2008), V3 (2009), V4 (2010–2011), QDSP6 V5 (2013, in Snapdragon 800[35]); and QDSP6 V6 (2016, in Snapdragon 820).[31] V4 has 20 DMIPS per milliwatt, operating at 500 MHz.[30][31] Clock speed of Hexagon varies in 400–2000 MHz for QDSP6 and in 256–350 MHz for previous generation of the architecture, the QDSP5.[36]

Versions of QDSP6 Process node, nm Date[17] Number of simultaneous threads Per-thread clock, MHz Total core clock, MHz Product
QDSP6 V1 65[17] Oct 2006
QDSP6 V2[37] 65 Dec 2007[17] 6 100 600
QDSP6 V3 (1st gen)[37] 45 2009 6 67 400
QDSP6 V3 (2nd gen)[37] 45 2009 4 100 400
QDSP6 V4[37] (V4M, V4C, V4L[17]) 28 2010–2011 3[18] 167 500
QDSP6 V5[38] (V5A, V5H[17]) 28 2013 3[17] 200 or greater with DMT[18] 600
642 14 2017 Snapdragon

630

QDSP6 V6 or 680[39] 14 2016/2017 4 500 2000 Snapdragon

820/821/636/660

682 10 2017 Snapdragon

835

683 11 2020 Snapdragon

460/662

685 10/11 2018-2020 4[40] (3 TOPS) Snapdragon

845/670/675/678/710/712

686 11/8 2019/2021 (3.3 TOPS) Snapdragon

665/480

688 8 2019/2020 (3.6 TOPS) Snapdragon

730(G)/732G

690 7 2019 (7 TOPS) Snapdragon

855/855+

692 8 2020 Snapdragon

720G/690

694 8 2020 (4.7 TOPS) Snapdragon

750G

696 7 2020 (5.4 TOPS) Snapdragon

765(G)/768G

698 7 2020 (15 TOPS) Snapdragon

865/865+

780 5 2021 (26 TOPS) Snapdragon

888

Availability in Snapdragon products[edit]

Both Hexagon (QDSP6) and pre-Hexagon (QDSP5) cores are used in modern Qualcomm SoCs, QDSP5 mostly in low-end products. Modem QDSPs (often pre-Hexagon) are not shown in the table.

QDSP5 usage:

Snapdragon generation Chipset (SoC) ID DSP Generation DSP Frequency, MHz Process node, nm
S1[36] MSM7627, MSM7227, MSM7625, MSM7225 QDSP5 320 65
S1[36] MSM7627A, MSM7227A, MSM7625A, MSM7225A QDSP5 350 45
S2[36] MSM8655, MSM8255, APQ8055, MSM7630, MSM7230 QDSP5 256 45
S4 Play[36] MSM8625, MSM8225 QDSP5 350 45
S200[41] 8110, 8210, 8610, 8112, 8212, 8612, 8225Q, 8625Q QDSP5 384 45 LP

QDSP6 (Hexagon) usage:

Snapdragon generation Chipset (SoC) ID QDSP6 version DSP Frequency, MHz Process node, nm
S1[36] QSD8650, QSD8250 QDSP6 600 65
S3[36] MSM8660, MSM8260, APQ8060 QDSP6 (V3?) 400 45
S4 Prime[36] MPQ8064 QDSP6 (V3?) 500 28
S4 Pro[36] MSM8960 Pro, APQ8064 QDSP6 (V3?) 500 28
S4 Plus[36] MSM8960, MSM8660A, MSM8260A, APQ8060A, MSM8930,
MSM8630, MSM8230, APQ8030, MSM8627, MSM8227
QDSP6 (V3?) 500 28
S400[41] 8926, 8930, 8230, 8630, 8930AB, 8230AB, 8630AB, 8030AB, 8226, 8626 QDSP6V4 500 28 LP
S600[41] 8064T, 8064M QDSP6V4 500 28 LP
S800[41] 8974, 8274, 8674, 8074 QDSP6V5A 600 28 HPm
S820[39] 8996 QDSP6V6 2000 14 FinFet LPP


Hardware codec supported[edit]

The different video codecs supported by the snapdragon SoCs.

D - decode; E - encode

FHD = FullHD = 1080p = 1920x1080px

HD = 720p which can be 1366x768px or 1280x720px

Snapdragon 200 series[edit]

The different video codecs supported by the snapdragon 200 series.

Codec Snapdragon

200[42]

Snapdragon

200[42]

Qualcomm

205[43]

Snapdragon

208/210[44]

Snapdragon

212[45]

Availability 2013 2013 2017 2014 2015
Hexagon QDSP5 QDSP6 536 536 536
H263 D & E D & E D & E D & E D & E
VC-1
H.264 D & E D & E D & E D & E D & E
H.264 10-bit - - - - -
VP8 D & E D & E D & E D & E D & E
H.265 D HD & E HD D HD & E HD D HD & E HD D FHD & E HD D FHD & E HD
H.265 10-bit - - - - -
H.265 12-bit - - - - -
VVC
VP9 - - - - -
VP9 10-bit - - - - -
AV1 - - - - -

Snapdragon 400 series[edit]

The different video codecs supported by the snapdragon 400 series.

Codec Snapdragon

400[46]

Snapdragon

410/415[47]

Snapdragon

425/427

Snapdragon

429/439[48]

Snapdragon

450[49]

Snapdragon

460[50]

Snapdragon

480[51]

Availability Q4 2013 2014/2015 Q1 2016/Q3 2017 Q2 2018 Q2 2017 Q1 2020 Q1 2021
Hexagon QDSP6 QDSP6 V5 536(256KB) 536 546 683
H263 D & E D & E D & E D & E D & E D & E D & E
VC-1
H.264 D & E D & E D & E D & E D & E D & E D & E
H.264 10-bit - - - - - - D & E
VP8 D & E D & E D & E D & E D & E D & E D & E
H.265 - D & E D & E D & E D & E D & E D & E
H.265 10-bit - - - - - -
H.265 12-bit - - - - - -
VVC - - - -| - -
VP9 - - - - D & E D & E
VP9 10-bit - - - - - -
AV1 - - - - - - -
Video frame rate

support Decoding

HD 60 fps
FHD 60 fps FHD 60 fps FHD 60 fps
Video frame

rate support

Encoding

HD 60 fps
FHD 60 fps FHD 60 fps FHD 60 fps

Snapdragon 600 series[edit]

The different video codecs supported by the snapdragon 600 series.

Codec Snapdragon 600[52] Snapdragon 610[53] Snapdragon 650/652/653 Snapdragon 630[54] Snapdragon 632[48] Snapdragon 636/660[54] Snapdragon 662[55] Snapdragon 665[56] Snapdragon 670[57] Snapdragon 690[58]
Availability Q1 2013 Q1 2015 Q2 2018 Q1 2020 Q2 2019 2019 Q2 2020
Hexagon QDSP6 V4 QDSP6 V50 QDSP6 V56 642 546 680 683 686 685 692
H263 D & E D & E D & E D & E D & E D & E D & E D & E D & E D & E
VC-1 D[59] & ?
H.264 D & E D & E D & E D & E D & E D & E D & E D & E D & E D & E
H.264 10-bit - - - - - - - - -
VP8 D & E D & E D & E D & E D & E D & E D & E D & E D & E D & E
H.265 - D & E D & E D & E D & E D & E D & E D & E D & E
H.265 10-bit - - - D & ? - D & ? - D & ? D & E
VVC - - - - - - - - - -
VP9 - - D[59] & ? D & E D & E D & E D & E D & E D & E D & E
VP9 10-bit - - - - - - - - -
AV1 - - - - - - - - - -
Video decoding frame rate support HD 60 fps HD 120 fps HD 240 fps[60] HD 240 fps HD 240 fps[61] HD 60 fps HD 240 fps HD 240 fps HD 240 fps
FHD 30 fps FHD 60 fps FHD 120 fps FHD 120 fps[60] FHD 120 fps FHD 120 fps[61] FHD 60 fps FHD 120 fps FHD 120 fps FHD 120 fps
No 4K No 4K 4K30 fps 4K30 fps[60] 4K30 fps 4K30 fps[61] No 4K 4K60 fps 4K60 fps[62] 4K60 fps
Video encoding frame rate support HD 60 fps HD 60 fps HD 240 fps[60] HD 240 fps HD 240 fps[61] HD 60 fps HD 240 fps HD 240 fps HD 240 fps
FHD 30 fps FHD 30 fps FHD 120 fps FHD 120 fps[60] FHD 120 fps FHD 120 fps[61] FHD 60 fps FHD 120 fps FHD 120 fps FHD 120 fps
No 4K No 4K 4K30 fps 4K30 fps[60] 4K30 fps 4K30 fps[61] No 4K 4K30 fps 4K30 fps 4K30 fps
Others

Snapdragon 700 series[edit]

The different video codecs supported by the snapdragon 700 series.

Codec Snapdragon

710[63]/712[64]

Snapdragon

720G[65]

Snapdragon

730G[66]/732G[67]

Snapdragon 765G 5G[68]

/765 5G[69]/768G 5G[70]

Availability TBA Q1 2020 ? ?
Hexagon 685 692 688 696[71]
H263 D & E D & E D & E D & E
VC-1 D & E D & E D & E D & E
H.264 D & E D & E D & E D & E
H.264 10-bit - - -
VP8 D & E D & E D & E D & E
H.265 D & E D & E D & E D & E
H.265 10-bit D D D D
H.265 12-bit - - - -
VVC - - - -
VP9 D & E D & E D & E D & E
VP9 10-bit D D D D
AV1 - - - -
Video frame

rate support

Decoding

HD 240 fps HD 240 fps HD 240 fps HD 480 fps
FHD 120 fps FHD 120 fps FHD 120 fps ?
4K 30fps 4K 30fps 4K 60fps 4K 60fps
Video frame

rate support

Encoding

HD 240 fps HD 240 fps HD 240 fps HD 480 fps
FHD 120 fps FHD 120 fps FHD 120 fps ?
4K 30fps 4K 30fps 4K 30fps ?
Others HDR10 HDR10, HLG HDR10 HDR10, HDR10+, HLG, Rec. 2020

Snapdragon 800 series[edit]

The different video codecs supported by the Snapdragon 800 series.

Codec Snapdragon

800[72]

Snapdragon

801[72]

Snapdragon

805[73]

Snapdragon

810[74]

Snapdragon

820/821[75]

Snapdragon

835

Snapdragon

845/850[76]

Snapdragon

855/855+[77]

Snapdragon

865/865+

/870[78]

Snapdragon

888[79]

Availability Q2 2013 Q1 2014 Q1 2014 Q3 2014 Q4 2015

Q3 2016

Q2 2017 Q1 2018 2019 2019

2021

Q4 2020
Hexagon QDSP6 V5 QDSP6 V5 QDSP6 V50 QDSP6 V56 680 682[80] 685[76] 690[81] 698 780
MPEG-4 D & E
H263 D & E[82]
VC-1 D & E
H.264 D & E[83]
H.264 10-bit N/A D & E
VP8 D & E [84]
H.265 N/A D & E 720P30 D & E
H.265 10-bit N/A D D D & E
VP9 D & E
VP9 10-bit D
AV1 N/A
VVC N/A
Decoding

FPS

HD@120 HD@240 HD@480[76] HD@480[85] HD@960
FHD@60 FHD@120 FHD@240[76] FHD@240 4K@120
4K@30 4K@60 8K@30
Encoding

FPS

HD@120 HD@240 HD@480[86] HD@480 HD@960
FHD@60 FHD@120 FHD@240[86] FHD@240 4K@120
4K@30 4K@60[86] 4K@60 8K@30
Others HDR10

Only decoding

HDR10, BT.2020

HLG[86]

HDR10+[81] HDR10+

Code sample[edit]

This is a single instruction packet from the inner loop of a FFT:[15][18]

{ R17:16 = MEMD(R0++M1)
  MEMD(R6++M1) = R25:24
  R20 = CMPY(R20, R8):<<1:rnd:sat
  R11:10 = VADDH(R11:10, R13:12)
}:endloop0

This packet is claimed by Qualcomm to be equal to 29 classic RISC operations; it includes vector add (4x 16-bit), complex multiply operation and hardware loop support. All instructions of the packet are done in the same cycle.

See also[edit]

References[edit]

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