Qualcomm Hexagon

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Hexagon
Designer Qualcomm
Bits 32-bit
Introduced 2006 (QDSP6)
Design 4-way multithreaded VLIW
Type Register-Register
Encoding Fixed 4 byte per instruction, up to 4 instructions in VLIW multiinstruction
Open proprietary
Registers
General purpose 32-bit GPR: 32, can be paired to 64-bit [1]

Hexagon (QDSP6) is a DSP based 32-bit multithreaded CPU architecture developed by Qualcomm. According to 2012 estimation, Qualcomm shipped 1.2 billion DSP cores inside its SoCs (average 2.3 DSP core per SoC) in 2011 year, and 1.5 billion cores were planned for 2012, making the QDSP most shipped architecture of DSP[2] (CEVA had around 1 billion of DSP cores shipped in 2011 with 90% of IP-licenseable DSP market[3]).

The Hexagon architecture is designed to deliver performance with low power over a variety of applications. It has features such as hardware assisted multithreading, privilege levels, VLIW, SIMD,[4] and instructions geared toward efficient signal processing. The CPU is capable of in-order dispatching up to 4 instructions (the packet) to 4 Execution Units every clock.[5][6] Hardware multithreading is implemented as barrel temporal multithreading - threads are switched in round-robin fashion each cycle, so 600 MHz physical core is presented as three logical 200 MHz cores before V5.[7][8] Hexagon V5 switched to dynamic multithreading (DMT) with thread switch on L2 misses, interrupt waiting or on special instructions.[8][9]

The port of Linux for Hexagon runs under a hypervisor layer ("Hexagon Virtual Machine"[10]) and was merged with the 3.2 release of the kernel.[11][12] The original hypervisor is closed-source, and in April 2013 a minimal open-source hypervisor implementation for QDSP6 V2 and V3, the "Hexagon MiniVM" was released by Qualcomm under a BSD-style license.[13][14]

Support for Hexagon was added in 3.1 release of LLVM by Tony Linthicum.[15] There is also a non-FSF maintained branch of GCC and binutils.[16]

Hexagon DSPs are included in Snapdragon SoC since 2006.[17][18] In Snapdragon S4 (MSM8960 and newer) there are three QDSP cores, two in the Modem subsystem and one Hexagon core in the Multimedia subsystem. Modem cores are programmed by Qualcomm only, and only Multimedia core is allowed to be programmed by user.

They are also used in some femtocell processors of Qualcomm, including FSM9832.[19]

Versions[edit]

There are four versions of QDSP6 architecture released: V1 (2006), V2 (2007-2008), V3 (2009), V4 (2010-2011); and QDSP6 V5 (2013, in Snapdragon 800[20]).[18] V4 has 20 DMIPS per milliwatt, operating at 500 MHz.[17][18] Clock speed of Hexagon varies in 400–600 MHz for QDSP6 and in 256–350 MHz for previous generation of the architecture, the QDSP5.[21]

Versions of QDSP6 Process node, nm Date[8] Number of simultaneous threads Per-thread clock, MHz Total core clock, MHz
QDSP6 V1 65[8] Oct 2006
QDSP6 V2[22] 65 Dec 2007[8] 6 100 600
QDSP6 V3 (1st gen)[22] 45 2009 6 67 400
QDSP6 V3 (2nd gen)[22] 45 2009 4 100 400
QDSP6 V4[22] (V4M, V4C, V4L[8]) 28 2010-2011 3[9] 167 500
QDSP6 V5[23] (V5A, V5H[8]) 28 2013 3[8] 200 or greater with DMT[9] 600

Availability in Snapdragon products[edit]

Both Hexagon (QDSP6) and pre-Hexagon (QDSP5) cores are used in modern Qualcomm SoCs, QDSP5 mostly in low-end products. Modem QDSPs (often pre-Hexagon) are not shown in the table.

QDSP5 usage:

Snapdragon generation Chipset (SoC) ID DSP Generation DSP Frequency, MHz Process node, nm
S1 [21] MSM7627, MSM7227, MSM7625, MSM7225 QDSP5 320 65
S1 [21] MSM7627A, MSM7227A, MSM7625A, MSM7225A QDSP5 350 45
S2 [21] MSM8655, MSM8255, APQ8055, MSM7630, MSM7230 QDSP5 256 45
S4 Play[21] MSM8625, MSM8225 QDSP5 350 45
S200[24] 8110, 8210, 8610, 8112, 8212, 8612, 8225Q, 8625Q QDSP5 384 45 LP

QDSP6 (Hexagon) usage:

Snapdragon generation Chipset (SoC) ID QDSP6 version DSP Frequency, MHz Process node, nm
S1 [21] QSD8650, QSD8250 QDSP6 600 65
S3 [21] MSM8660, MSM8260, APQ8060 QDSP6 (V3?) 400 45
S4 Prime [21] MPQ8064 QDSP6 (V4?) 500 28
S4 Pro [21] MSM8960 Pro, APQ8064 QDSP6 (V4?) 500 28
S4 Plus [21] MSM8960, MSM8660A, MSM8260A, APQ8060A, MSM8930,
MSM8630, MSM8230, APQ8030, MSM8627, MSM8227
QDSP6 (V4?) 500 28
S400[24] 8926, 8930, 8230, 8630, 8930AB, 8230AB, 8630AB, 8030AB, 8226, 8626 QDSP6V4 500 28 LP
S600[24] 8064T, 8064M QDSP6V4 500 28 LP
S800[24] 8974, 8274, 8674, 8074 QDSP6V5A 600 28 HPm

Code sample[edit]

This is a single instruction packet from the inner loop of a FFT:[6][9]

{ R17:16 = MEMD(R0++M1)
  MEMD(R6++M1) = R25:24
  R20 = CMPY(R20, R8):<<1:rnd:sat
  R11:10 = VADDH(R11:10, R13:12)
}:endloop0

This packet is claimed by Qualcomm to be equal to 29 classic RISC operations; it includes vector add (4x 16-bit), complex multiply operation and hardware loop support. All instructions of the packet are done in the same cycle.

See also[edit]

References[edit]

  1. ^ Baseband exploitation in 2013: Hexagon challenges /Ralf-Philipp Weinmann Pacsec 20132013-11-14, Tokyo, Japan: "32-bit unified address space for code and data – Byte addressable; 32 General registers (32-bit) – also usable pairwise: 64-bit register pairs"
  2. ^ Will Strauss, Forward Concepts. Wireless/DSP Market Bulletin: Qualcomm Leads in Global DSP Silicon Shipments // Forward Concepts: "In calendar year 2011, Qualcomm shipped a reported 521 million MSM chip shipments and we estimate that an average of 2.3 of its DSP cores in each unit resulted in 1.2 billion DSPs shipped in silicon. This (calendar) year, we estimate that the company will ship an average of 2.4 DSP cores with each (more complex) MSM chip."
  3. ^ [1]; [2]; Ceva grabs 90% of DSP IP market, 2012
  4. ^ Hexagon v2 Programmers Reference
  5. ^ "Rob Landley's Blog Thing for 2012". Landley.net. Retrieved 2012-10-19. 
  6. ^ a b Porting LLVM to a Next Generation DSP, L. Taylor Simpson (Qualcomm) // LLVM Developers’ Meeting: 11/18/2011
  7. ^ Faster 128-EEA3 and 128-EIA3 Software, Roberto Avanzi and Billy Bob Brumley (Qualcomm Research), Cryptology ePrint Archive: Report 2013/428, 2 Jul 2013. Page 9.
  8. ^ a b c d e f g h Qualcomm Hexagon DSP: An architecture optimized for mobile multimedia and communications // Lucian Codrescu (Qualcomm), Hot Chips 25, Palo Alto, CA, August 2013.
  9. ^ a b c d Qualcomm Extends Hexagon DSP: Hexagon v5 Adds Floating-Point Math, Dynamic Multithreading // Linley Gwennap, Microprocessor Report, August 2013
  10. ^ https://developer.qualcomm.com/download/80-nb419-3ahexagonvirtualmachinespec.pdf (restricted access)
  11. ^ "3.2 merge window, part 1". lwn.net. Retrieved 2012-10-19. 
  12. ^ Linux Kernel 3.2 Release Notes "1.4. New architecture: Hexagon"
  13. ^ Richard Kuo, Hexagon MiniVM // linux.ports.hexagon, 25 Apr 2013
  14. ^ Hexagon MiniVM // CodeAurora (Qualcomm)
  15. ^ "LLVM 3.1 Release Notes". Llvm.org. 2012-05-15. Retrieved 2012-10-19. 
  16. ^ "Hexagon Project Wiki". Codeaurora.org.  " "Hexagon download". 
  17. ^ a b Qualcomm Announces Its 2012 Superchip: 28nm Snapdragon S4, 10/12/2011 by John Oram. Quote: "Hexagon DSPs have been in Snapdragon chips since 2006."
  18. ^ a b c QDSP6 V4: Qualcomm Gives Customers and Developers Programming Access to its DSP Core // InsideDSP, June 22, 2012
  19. ^ Qualcomm Aims Hexagon at Femtocells, October 31, 2011. Linley Gwennap// Linley WIRE
  20. ^ Qualcomm Announces Next Generation Snapdragon Premium Mobile Processors // Qualcomm, January 07, 2013
  21. ^ a b c d e f g h i j "List of Snapdragon SoCs". Developer.qualcomm.com. Retrieved 2012-10-19. 
  22. ^ a b c d QDSP6 V4: BDTI Benchmark Results and Implementation Details Of Qualcomm's DSP Core // BDTI, February 12, 2013
  23. ^ Qualcomm's QDSP6 v5: Benchmarking Results Confirm That Floating-Point Support Has Arrived // BDTI, June 12, 2013
  24. ^ a b c d Snapdragon 800, 600, 400, 200 Processor Specs // Qualcomm

External links[edit]