The Roofline model is an intuitive visual performance model used to provide performance estimates of a given compute kernel or application running on multi-core, many-core, or accelerator processor architectures, by showing inherent hardware limitations, and potential benefit and priority of optimizations. By combining locality, bandwidth, and different parallelization paradigms into a single performance figure, the model can be an effective alternative to assess the quality of attained performance instead of using simple percent-of-peak estimates, as it provides insights on both the implementation and inherent performance limitations.
The most basic Roofline model can be visualized by plotting floating-point performance as a function of machine peak performance[vague][clarification needed], machine peak bandwidth, and arithmetic intensity. The resultant curve is effectively a performance bound under which kernel or application performance exists, and includes two platform-specific performance ceilings[clarification needed]: a ceiling derived from the memory bandwidth and one derived from the processor's peak performance (see figure on the right).
Related terms and performance metrics
The work denotes the number of operations performed by a given kernel or application. This metric may refer to any type of operation, from number of array points updated, to number of integer operations, to number of floating point operations (FLOPs), and the choice of one or another is driven by convenience. In the majority of the cases however, is expressed as FLOPs.
Note that the work is a property of the given kernel or application and thus depend just partially on the platform characteristics.
The memory traffic denotes the number of bytes of memory transfers incurred during the execution of the kernel or application. In contrast to , is heavily dependent on the properties of the chosen platform, such as for instance the structure of the cache hierarchy.
The naïve Roofline is obtained by applying simple bound and bottleneck analysis. In this formulation of the Roofline model, there are only two parameters, the peak performance and the peak bandwidth of the specific architecture, and one variable, the arithmetic intensity. The peak performance, in general expressed as GFLOPS, can be usually derived from architectural manuals, while the peak bandwidth, that references to peak DRAM bandwidth to be specific, is instead obtained via benchmarking. The resulting plot, in general with both axes in logarithmic scale, is then derived by the following formula:
A given kernel or application is then characterized by a point given by its arithmetic intensity (on the x-axis). The attainable performance is then computed by drawing a vertical line that hits the Roofline curve. Hence. the kernel or application is said to be memory-bound if . Conversely, if , the computation is said to be compute-bound.
Adding ceilings to the model
The naive Roofline provides just an upper bound (the theoretical maximum) to performance. Although it can still give useful insights on the attainable performance, it does not provide a complete picture of what is actually limiting it. If, for instance, the considered kernel or application performs far below the Roofline, it might be useful to capture other performance ceilings, other than simple peak bandwidth and performance, to better guide the programmer on which optimization to implement, or even to assess the suitability of the architecture used with respect to the analyzed kernel or application. The added ceilings impose then a limit on the attainable performance that is below the actual Roofline, and indicate that the kernel or application cannot break through anyone of these ceilings without first performing the associated optimization.
The Roofline plot can be expanded upon three different aspects: communication, adding the bandwidth ceilings; computation, adding the so-called in-core ceilings; and locality, adding the locality walls.
An example Roofline model with locality walls. The wall labeled as 3 C's denotes the presence all three types of cache misses: compulsory, capacity and conflict misses. The wall labeled as 2 C's represent the presence of either compulsory and capacity or compulsory and conflict misses. The last wall denotes the presence of just compulsory misses.
The bandwidth ceilings are bandwidth diagonals placed below the idealized peak bandwidth diagonal. Their existence is due to the lack of some kind of memory related architectural optimization, such as cache coherence, or software optimization, such as poor exposure of concurrency (that in turn limit bandwidth usage).
The in-core ceilings are roofline-like curve beneath the actual roofline that may be present due to the lack of some form of parallelism. These ceilings effectively limit how high performance can reach. Performance cannot exceed an in-core ceiling until the underlying lack of parallelism is expressed and exploited. The ceilings can be also derived from architectural optimization manuals other than benchmarks.
If the ideal assumption that arithmetic intensity is solely a function of the kernel is removed, and the cache topology - and therefore cache misses - is taken into account, the arithmetic intensity clearly becomes dependent on a combination of kernel and architecture. This may result in a degradation in performance depending on the balance between the resultant arithmetic intensity and the ridge point. Unlike "proper" ceilings, the resulting lines on the Roofline plot are vertical barriers through which arithmetic intensity cannot pass without optimization. For this reason, they are referenced to as locality walls or arithmetic intensity walls.
Extension of the model
Since its introduction, the model has been further extended to account for a broader set of metrics and hardware-related bottlenecks. Already available in literature there are extensions that take into account the impact of NUMA organization of memory, of out-of-order execution, of memory latencies, and to model at a finer grain the cache hierarchy in order to better understand what is actually limiting performance and drive the optimization process.
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- Williams, Samuel W. (2008). Auto-tuning Performance on Multicore Computers (Ph.D.). University of California at Berkeley.
- Williams, Samuel; Waterman, Andrew; Patterson, David (2009-04-01). "Roofline: An Insightful Visual Performance Model for Multicore Architectures". Commun. ACM. 52 (4): 65–76. doi:10.1145/1498765.1498785. ISSN 0001-0782.
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- Lorenzo, Oscar G.; Pena, Tomás F.; Cabaleiro, José C.; Pichel, Juan C.; Rivera, Francisco F. (2014-03-31). "Using an extended Roofline Model to understand data and thread affinities on NUMA systems". Annals of Multicore and GPU Programming. 1 (1): 56–67. ISSN 2341-3158.
- "Roofline Performance Model". Lawrence Berkeley National Laboratory. Retrieved 19 June 2016.
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- da Silva, Bruno; Braeken, An; D'Hollander, Erik H.; Touhafi, Abdellah (2013-01-01). "Performance Modeling for FPGAs: Extending the Roofline Model with High-level Synthesis Tools". International Journal of Reconfigurable Computing. 2013: 1–10. doi:10.1155/2013/428078. ISSN 1687-7195.
- The Roofline Model: A Pedagogical Tool for Auto-tuning Kernels on Multicore Architectures
- Applying the Roofline model
- Extending the Roofline Model: Bottleneck Analysis with Microarchitectural Constraints
- Roofline Model Toolkit
- Roofline Model Toolkit: A Practical Tool for Architectural and Program Analysis - publication related to the tool.
- Extended Roofline Model
- Intel Advisor - Roofline model automation
- Youtube Video on how to use Intel Advisor Roofline