Root complex

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An example of the PCI Express topology, displaying the position of a root complex.[1]

In a PCI Express (PCIe) system, a root complex device connects the CPU and memory subsystem to the PCI Express switch fabric composed of one or more switch devices.

Similar to a host bridge in a PCI system,[2] the root complex generates transaction requests on behalf of the CPU, which is interconnected through a local bus. Root complex functionality may be implemented as a discrete device (northbridge chip), or may be integrated in the CPU. A root complex may contain more than one PCI Express port and multiple switch devices can be connected to ports on the root complex or cascaded.[3]

Device Memory Map[edit]

The PCIE Root Complex holds a master copy of a 'Type 1 Configuration Table' that defines the host memory space that is accessible from each Endpoint device. In addition, each PCIE Endpoint device holds a master copy of their own memory space map in the host system memory as a 'Type 0 Configuration Table', this configuration table in each device allows the host to access the local memory of a PCIe device. Both the Type 1 and Type 0 configuration tables are setup by the Host Operating System that controls the Root Complex by a process known as enumeration and which acts to build a device memory map for the system by querying each bridge, and endpoint device connected on the bus network. Similarly, a PCIE Bridge acts a tiered rootcomplex with a "Type 0 Configuration Table"

References[edit]

  1. ^ Richard Solomon (2015-06-17). "PCI Express Basics and Background" (PDF). PCI-SIG. p. 26. Retrieved 2016-04-12. CS1 maint: discouraged parameter (link)
  2. ^ "Bus Specifics (Writing Device Drivers)". docs.oracle.com. Retrieved 2020-11-14.
  3. ^ "Choosing the Right Programmable Logic Solution for PCI Express Applications". Archived from the original on 21 February 2011. Retrieved 31 March 2010. CS1 maint: discouraged parameter (link)